X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fprodrive%2Fp3p440%2Fp3p440.c;h=9a078527609ea71caf505a1726902dc7c479c70e;hb=f8450829f921cf10667af98a8d08edfa3d998f04;hp=1a8aacbdf12dbddf1cdf772c49b5c9c21ef24c0d;hpb=8e990cb076a1c77daf3a50cc0df9732135e9eef5;p=u-boot

diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c
index 1a8aacbdf1..9a07852760 100644
--- a/board/prodrive/p3p440/p3p440.c
+++ b/board/prodrive/p3p440/p3p440.c
@@ -35,29 +35,29 @@ void set_led(int color)
 {
 	switch (color) {
 	case LED_OFF:
-		out32(GPIO0_OR,  in32(GPIO0_OR) & ~CFG_LED_GREEN & ~CFG_LED_RED);
+		out32(GPIO0_OR,  in32(GPIO0_OR) & ~CONFIG_SYS_LED_GREEN & ~CONFIG_SYS_LED_RED);
 		break;
 
 	case LED_GREEN:
-		out32(GPIO0_OR,  (in32(GPIO0_OR) | CFG_LED_GREEN) & ~CFG_LED_RED);
+		out32(GPIO0_OR,  (in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN) & ~CONFIG_SYS_LED_RED);
 		break;
 
 	case LED_RED:
-		out32(GPIO0_OR,  (in32(GPIO0_OR) | CFG_LED_RED) & ~CFG_LED_GREEN);
+		out32(GPIO0_OR,  (in32(GPIO0_OR) | CONFIG_SYS_LED_RED) & ~CONFIG_SYS_LED_GREEN);
 		break;
 
 	case LED_ORANGE:
-		out32(GPIO0_OR,  in32(GPIO0_OR) | CFG_LED_GREEN | CFG_LED_RED);
+		out32(GPIO0_OR,  in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN | CONFIG_SYS_LED_RED);
 		break;
 	}
 }
 
 static int is_monarch(void)
 {
-	out32(GPIO0_OR,  in32(GPIO0_OR) & ~CFG_GPIO_RDY);
+	out32(GPIO0_OR,  in32(GPIO0_OR) & ~CONFIG_SYS_GPIO_RDY);
 	udelay(1000);
 
-	if (in32(GPIO0_IR) & CFG_MONARCH_IO)
+	if (in32(GPIO0_IR) & CONFIG_SYS_MONARCH_IO)
 		return 0;
 	else
 		return 1;
@@ -68,11 +68,11 @@ static void wait_for_pci_ready(void)
 	/*
 	 * Configure EREADY_IO as input
 	 */
-	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_EREADY_IO);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_EREADY_IO);
 	udelay(1000);
 
 	for (;;) {
-		if (in32(GPIO0_IR) & CFG_EREADY_IO)
+		if (in32(GPIO0_IR) & CONFIG_SYS_EREADY_IO)
 			return;
 	}
 
@@ -85,37 +85,37 @@ int board_early_init_f(void)
 	/*--------------------------------------------------------------------
 	 * Setup the external bus controller/chip selects
 	 *-------------------------------------------------------------------*/
-	mtdcr(ebccfga, xbcfg);
-	reg = mfdcr(ebccfgd);
-	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */
+	mtdcr(EBC0_CFGADDR, EBC0_CFG);
+	reg = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGDATA, reg | 0x04000000);	/* Set ATC */
 
 	/*--------------------------------------------------------------------
 	 * Setup pin multiplexing (GPIO/IRQ...)
 	 *-------------------------------------------------------------------*/
-	mtdcr(cpc0_gpio, 0x03F01F80);
+	mtdcr(CPC0_GPIO, 0x03F01F80);
 
 	out32(GPIO0_ODR, 0x00000000);	/* no open drain pins      */
-	out32(GPIO0_TCR, CFG_GPIO_RDY | CFG_EREADY_IO | CFG_LED_RED | CFG_LED_GREEN);
-	out32(GPIO0_OR,  CFG_GPIO_RDY);
+	out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN);
+	out32(GPIO0_OR,  CONFIG_SYS_GPIO_RDY);
 
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000001);	/* UIC1 crit is critical */
-	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000001);	/* UIC1 crit is critical */
+	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 
 	return 0;
 }
@@ -152,13 +152,13 @@ int misc_init_r (void)
 	/*
 	 * Check if only one FLASH bank is available
 	 */
-	if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
-		mtebc(pb1cr, 0);			/* disable cs */
-		mtebc(pb1ap, 0);
-		mtebc(pb2cr, 0);			/* disable cs */
-		mtebc(pb2ap, 0);
-		mtebc(pb3cr, 0);			/* disable cs */
-		mtebc(pb3ap, 0);
+	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
+		mtebc(PB1CR, 0);			/* disable cs */
+		mtebc(PB1AP, 0);
+		mtebc(PB2CR, 0);			/* disable cs */
+		mtebc(PB2AP, 0);
+		mtebc(PB3CR, 0);			/* disable cs */
+		mtebc(PB3AP, 0);
 	}
 
 	return 0;
@@ -185,7 +185,7 @@ int pci_pre_init(struct pci_controller *hose)
 	 *	The P3P440 board is always configured as the host & requires the
 	 *	PCI arbiter to be disabled because it's an PMC module.
 	 *--------------------------------------------------------------------------*/
-	strap = mfdcr(cpc0_strp1);
+	strap = mfdcr(CPC0_STRP1);
 	if (strap & 0x00100000) {
 		printf("PCI: CPC0_STRP1[PAE] set.\n");
 		return 0;
@@ -203,36 +203,36 @@ int pci_pre_init(struct pci_controller *hose)
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
 	/*--------------------------------------------------------------------------+
 	 * Disable everything
 	 *--------------------------------------------------------------------------*/
-	out32r(PCIX0_PIM0SA, 0);	/* disable */
-	out32r(PCIX0_PIM1SA, 0);	/* disable */
-	out32r(PCIX0_PIM2SA, 0);	/* disable */
-	out32r(PCIX0_EROMBA, 0);	/* disable expansion rom */
+	out32r(PCIL0_PIM0SA, 0);	/* disable */
+	out32r(PCIL0_PIM1SA, 0);	/* disable */
+	out32r(PCIL0_PIM2SA, 0);	/* disable */
+	out32r(PCIL0_EROMBA, 0);	/* disable expansion rom */
 
 	/*--------------------------------------------------------------------------+
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 	 * options to not support sizes such as 128/256 MB.
 	 *--------------------------------------------------------------------------*/
-	out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
-	out32r(PCIX0_PIM0LAH, 0);
-	out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+	out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+	out32r(PCIL0_PIM0LAH, 0);
+	out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
 
-	out32r(PCIX0_BAR0, 0);
+	out32r(PCIL0_BAR0, 0);
 
 	/*--------------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *--------------------------------------------------------------------------*/
-	out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
-	out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
+	out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
-	out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+	out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 /*************************************************************************
  *  is_pci_host