X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Frbc823%2Frbc823.c;h=ddfba14919946a349fde9f2e26d451fa172fe11c;hb=959278083db4a2f104e56069ca031ecc3213c728;hp=9e60c2b646978beb3193740a2bc537f4e0610aa9;hpb=ea1fba136a4778b8f55e6b94a76a548cfad9f522;p=u-boot

diff --git a/board/rbc823/rbc823.c b/board/rbc823/rbc823.c
index 9e60c2b646..ddfba14919 100644
--- a/board/rbc823/rbc823.c
+++ b/board/rbc823/rbc823.c
@@ -127,24 +127,25 @@ const uint static_table[] =
 
 int checkboard (void)
 {
-	char *s = getenv ("serial#");
+	char buf[64];
+	int i = getenv_f("serial#", buf, sizeof(buf));
 
-	if (!s || strncmp (s, "TQM8", 4)) {
+	if (i < 0 || strncmp(buf, "TQM8", 4)) {
 		printf ("### No HW ID - assuming RBC823\n");
 		return (0);
 	}
 
-	puts (s);
-	putc ('\n');
+	puts(buf);
+	putc('\n');
 
 	return (0);
 }
 
 /* ------------------------------------------------------------------------- */
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size_b0, size8, size9;
 
@@ -154,15 +155,15 @@ long int initdram (int board_type)
 	/*
 	 * 1 Bank of 64Mbit x 2 devices
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
 	memctl->memc_mar = 0x00000088;
 
 	/*
 	 * Map controller SDRAM bank 0
 	 */
-	memctl->memc_or4 = CFG_OR4_PRELIM;
-	memctl->memc_br4 = CFG_BR4_PRELIM;
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
+	memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 	udelay (200);
 
 	/*
@@ -170,11 +171,11 @@ long int initdram (int board_type)
 	 */
 	memctl->memc_mcr = 0x80008105;	/* SDRAM bank 0 */
 	udelay (1);
-	memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
+	memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
 	udelay (200);
 	memctl->memc_mcr = 0x80008130;	/* SDRAM bank 0 - execute twice */
 	udelay (1);
-	memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
+	memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
 	udelay (200);
 
 	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
@@ -186,21 +187,21 @@ long int initdram (int board_type)
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;	/* 16: but should be: CFG_MPTPR_1BK_4K */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;	/* 16: but should be: CONFIG_SYS_MPTPR_1BK_4K */
 
 	/*
 	 * Check Bank 0 Memory Size for re-configuration
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM,
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM,
 			   SDRAM_MAX_SIZE);
 	udelay (1000);
 
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM,
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM,
 			   SDRAM_MAX_SIZE);
 
 	if (size8 < size9) {	/* leave configuration at 9 columns     */
@@ -208,7 +209,7 @@ long int initdram (int board_type)
 /*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
 	} else {		/* back to 8 columns                    */
 		size_b0 = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 		udelay (500);
 /*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
 	}
@@ -221,14 +222,14 @@ long int initdram (int board_type)
 	 */
 	if ((size_b0 < 0x02000000)) {
 		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 		udelay (1000);
 	}
 
 	/* SDRAM Bank 0 is bigger - map first       */
 
-	memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-	memctl->memc_br4 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br4 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 	udelay (10000);
 
@@ -248,7 +249,7 @@ long int initdram (int board_type)
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
@@ -256,9 +257,10 @@ static long int dram_size (long int mamr_value, long int *base,
 	return (get_ram_size (base, maxsize));
 }
 
+#ifdef CONFIG_CMD_DOC
 void doc_init (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	upmconfig (UPMB, (uint *) static_table,
@@ -267,3 +269,4 @@ void doc_init (void)
 
 	doc_probe (FLASH_BASE1_PRELIM);
 }
+#endif