X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Frenesas%2Frsk7203%2Flowlevel_init.S;h=30ef5abeddba8816058540ce3020694416a0f656;hb=f69b980d108b5f15ca7dd3f4284d5a66488c3625;hp=e4d6f9e7dfda267f7f1aaf9508d3af96315ede21;hpb=b24ef56587a2a9295de55e526a365e6af3ab2581;p=u-boot diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S index e4d6f9e7df..30ef5abedd 100644 --- a/board/renesas/rsk7203/lowlevel_init.S +++ b/board/renesas/rsk7203/lowlevel_init.S @@ -21,6 +21,7 @@ #include #include +#include .global lowlevel_init @@ -29,153 +30,89 @@ lowlevel_init: /* Cache setting */ - mov.l CCR1_A ,r1 - mov.l CCR1_D ,r0 - mov.l r0,@r1 + write32 CCR1_A ,CCR1_D /* ConfigurePortPins */ - mov.l PECRL3_A, r1 - mov.l PECRL3_D, r0 - mov.w r0,@r1 + write16 PECRL3_A, PECRL3_D - mov.l PCCRL4_A, r1 - mov.l PCCRL4_D0, r0 - mov.w r0,@r1 + write16 PCCRL4_A, PCCRL4_D0 - mov.l PECRL4_A, r1 - mov.l PECRL4_D0, r0 - mov.w r0,@r1 + write16 PECRL4_A, PECRL4_D0 - mov.l PEIORL_A, r1 - mov.l PEIORL_D0, r0 - mov.w r0,@r1 + write16 PEIORL_A, PEIORL_D0 - mov.l PCIORL_A, r1 - mov.l PCIORL_D, r0 - mov.w r0,@r1 + write16 PCIORL_A, PCIORL_D - mov.l PFCRH2_A, r1 - mov.l PFCRH2_D, r0 - mov.w r0,@r1 + write16 PFCRH2_A, PFCRH2_D - mov.l PFCRH3_A, r1 - mov.l PFCRH3_D, r0 - mov.w r0,@r1 + write16 PFCRH3_A, PFCRH3_D - mov.l PFCRH1_A, r1 - mov.l PFCRH1_D, r0 - mov.w r0,@r1 + write16 PFCRH1_A, PFCRH1_D - mov.l PFIORH_A, r1 - mov.l PFIORH_D, r0 - mov.w r0,@r1 + write16 PFIORH_A, PFIORH_D - mov.l PECRL1_A, r1 - mov.l PECRL1_D0, r0 - mov.w r0,@r1 + write16 PECRL1_A, PECRL1_D0 - mov.l PEIORL_A, r1 - mov.l PEIORL_D1, r0 - mov.w r0,@r1 + write16 PEIORL_A, PEIORL_D1 /* Configure Operating Frequency */ - mov.l WTCSR_A ,r1 - mov.l WTCSR_D0 ,r0 - mov.w r0,@r1 + write16 WTCSR_A, WTCSR_D0 - mov.l WTCSR_A ,r1 - mov.l WTCSR_D1 ,r0 - mov.w r0,@r1 + write16 WTCSR_A, WTCSR_D1 - mov.l WTCNT_A ,r1 - mov.l WTCNT_D ,r0 - mov.w r0,@r1 + write16 WTCNT_A, WTCNT_D /* Set clock mode*/ - mov.l FRQCR_A,r1 - mov.l FRQCR_D,r0 - mov.w r0,@r1 + write16 FRQCR_A, FRQCR_D /* Configure Bus And Memory */ init_bsc_cs0: - mov.l PCCRL4_A,r1 - mov.l PCCRL4_D1,r0 - mov.w r0,@r1 + write16 PCCRL4_A, PCCRL4_D1 - mov.l PECRL1_A,r1 - mov.l PECRL1_D1,r0 - mov.w r0,@r1 + write16 PECRL1_A, PECRL1_D1 - mov.l CMNCR_A,r1 - mov.l CMNCR_D,r0 - mov.l r0,@r1 + write32 CMNCR_A, CMNCR_D - mov.l SC0BCR_A,r1 - mov.l SC0BCR_D,r0 - mov.l r0,@r1 + write32 CS0BCR_A, CS0BCR_D - mov.l CS0WCR_A,r1 - mov.l CS0WCR_D,r0 - mov.l r0,@r1 + write32 CS0WCR_A, CS0WCR_D init_bsc_cs1: - mov.l PECRL4_A,r1 - mov.l PECRL4_D1,r0 - mov.w r0,@r1 + write16 PECRL4_A, PECRL4_D1 - mov.l CS1WCR_A,r1 - mov.l CS1WCR_D,r0 - mov.l r0,@r1 + write32 CS1WCR_A, CS1WCR_D init_sdram: - mov.l PCCRL2_A,r1 - mov.l PCCRL2_D,r0 - mov.w r0,@r1 + write16 PCCRL2_A, PCCRL2_D - mov.l PCCRL4_A,r1 - mov.l PCCRL4_D2,r0 - mov.w r0,@r1 + write16 PCCRL4_A, PCCRL4_D2 - mov.l PCCRL1_A,r1 - mov.l PCCRL1_D,r0 - mov.w r0,@r1 + write16 PCCRL1_A, PCCRL1_D - mov.l PCCRL3_A,r1 - mov.l PCCRL3_D,r0 - mov.w r0,@r1 + write16 PCCRL3_A, PCCRL3_D - mov.l CS3BCR_A,r1 - mov.l CS3BCR_D,r0 - mov.l r0,@r1 + write32 CS3BCR_A, CS3BCR_D - mov.l CS3WCR_A,r1 - mov.l CS3WCR_D,r0 - mov.l r0,@r1 + write32 CS3WCR_A, CS3WCR_D - mov.l SDCR_A,r1 - mov.l SDCR_D,r0 - mov.l r0,@r1 + write32 SDCR_A, SDCR_D - mov.l RTCOR_A,r1 - mov.l RTCOR_D,r0 - mov.l r0,@r1 + write32 RTCOR_A, RTCOR_D - mov.l RTCSR_A,r1 - mov.l RTCSR_D,r0 - mov.l r0,@r1 + write32 RTCSR_A, RTCSR_D /* wait 200us */ - mov.l REPEAT_D,r3 - mov #0,r2 + mov.l REPEAT_D, r3 + mov #0, r2 repeat0: - add #1,r2 - cmp/hs r3,r2 - bf repeat0 + add #1, r2 + cmp/hs r3, r2 + bf repeat0 nop - mov.l SDRAM_MODE, r1 - mov #0,r0 - mov.l r0, @r1 + mov.l SDRAM_MODE, r1 + mov #0, r0 + mov.l r0, @r1 nop rts @@ -185,63 +122,82 @@ repeat0: CCR1_A: .long CCR1 CCR1_D: .long 0x0000090B PCCRL4_A: .long 0xFFFE3910 -PCCRL4_D0: .long 0x00000000 +PCCRL4_D0: .word 0x0000 +.align 2 PECRL4_A: .long 0xFFFE3A10 -PECRL4_D0: .long 0x00000000 +PECRL4_D0: .word 0x0000 +.align 2 PECRL3_A: .long 0xFFFE3A12 -PECRL3_D: .long 0x00000000 +PECRL3_D: .word 0x0000 +.align 2 PEIORL_A: .long 0xFFFE3A06 -PEIORL_D0: .long 0x00001C00 -PEIORL_D1: .long 0x00001C02 +PEIORL_D0: .word 0x1C00 +PEIORL_D1: .word 0x1C02 PCIORL_A: .long 0xFFFE3906 -PCIORL_D: .long 0x00004000 +PCIORL_D: .word 0x4000 +.align 2 PFCRH2_A: .long 0xFFFE3A8C -PFCRH2_D: .long 0x00000000 +PFCRH2_D: .word 0x0000 +.align 2 PFCRH3_A: .long 0xFFFE3A8A -PFCRH3_D: .long 0x00000000 +PFCRH3_D: .word 0x0000 +.align 2 PFCRH1_A: .long 0xFFFE3A8E -PFCRH1_D: .long 0x00000000 +PFCRH1_D: .word 0x0000 +.align 2 PFIORH_A: .long 0xFFFE3A84 -PFIORH_D: .long 0x00000729 +PFIORH_D: .word 0x0729 +.align 2 PECRL1_A: .long 0xFFFE3A16 -PECRL1_D0: .long 0x00000033 +PECRL1_D0: .word 0x0033 +.align 2 WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .long 0x0000A518 -WTCSR_D1: .long 0x0000A51D +WTCSR_D0: .word 0xA518 +WTCSR_D1: .word 0xA51D WTCNT_A: .long 0xFFFE0002 -WTCNT_D: .long 0x00005A84 +WTCNT_D: .word 0x5A84 +.align 2 FRQCR_A: .long 0xFFFE0010 -FRQCR_D: .long 0x00000104 +FRQCR_D: .word 0x0104 +.align 2 -PCCRL4_D1: .long 0x00000010 -PECRL1_D1: .long 0x00000133 +PCCRL4_D1: .word 0x0010 +PECRL1_D1: .word 0x0133 CMNCR_A: .long 0xFFFC0000 CMNCR_D: .long 0x00001810 -SC0BCR_A: .long 0xFFFC0004 -SC0BCR_D: .long 0x10000400 +CS0BCR_A: .long 0xFFFC0004 +CS0BCR_D: .long 0x10000400 CS0WCR_A: .long 0xFFFC0028 CS0WCR_D: .long 0x00000B41 -PECRL4_D1: .long 0x00000100 +PECRL4_D1: .word 0x0100 +.align 2 CS1WCR_A: .long 0xFFFC002C CS1WCR_D: .long 0x00000B01 -PCCRL4_D2: .long 0x00000011 +PCCRL4_D2: .word 0x0011 +.align 2 PCCRL3_A: .long 0xFFFE3912 -PCCRL3_D: .long 0x00000011 +PCCRL3_D: .word 0x0011 +.align 2 PCCRL2_A: .long 0xFFFE3914 -PCCRL2_D: .long 0x00001111 +PCCRL2_D: .word 0x1111 +.align 2 PCCRL1_A: .long 0xFFFE3916 -PCCRL1_D: .long 0x00001010 +PCCRL1_D: .word 0x1010 PDCRL4_A: .long 0xFFFE3990 -PDCRL4_D: .long 0x00000011 +PDCRL4_D: .word 0x0011 +.align 2 PDCRL3_A: .long 0xFFFE3992 -PDCRL3_D: .long 0x00000011 +PDCRL3_D: .word 0x00011 +.align 2 PDCRL2_A: .long 0xFFFE3994 -PDCRL2_D: .long 0x00001111 +PDCRL2_D: .word 0x1111 +.align 2 PDCRL1_A: .long 0xFFFE3996 -PDCRL1_D: .long 0x00001000 +PDCRL1_D: .word 0x1000 +.align 2 CS3BCR_A: .long 0xFFFC0010 CS3BCR_D: .long 0x00004400 CS3WCR_A: .long 0xFFFC0034 @@ -253,13 +209,5 @@ RTCOR_D: .long 0xA55A0041 RTCSR_A: .long 0xFFFC0050 RTCSR_D: .long 0xa55a0010 -STBCR3_A: .long 0xFFFE0408 -STBCR3_D: .long 0x00000000 -STBCR4_A: .long 0xFFFE040C -STBCR4_D: .long 0x00000008 -STBCR5_A: .long 0xFFFE0410 -STBCR5_D: .long 0x00000000 -STBCR6_A: .long 0xFFFE0414 -STBCR6_D: .long 0x00000002 SDRAM_MODE: .long 0xFFFC5040 REPEAT_D: .long 0x00009C40