X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fsacsng%2Fsacsng.c;h=49d8bba15de0d10f9d874306d4bdc8e60b4cf413;hb=5f4d36825a028e300b7d56a566d2cf84418b7a68;hp=086e42a6a703b2e7cd473e9611bd787f7a023f4d;hpb=8bde7f776c77b343aca29b8c7b58464d915ac245;p=u-boot diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c index 086e42a6a7..49d8bba15d 100644 --- a/board/sacsng/sacsng.c +++ b/board/sacsng/sacsng.c @@ -22,17 +22,24 @@ * MA 02111-1307 USA */ -#include #include +#include #include #include #include #include +#include #ifdef CONFIG_SHOW_BOOT_PROGRESS #include #endif +#ifdef CONFIG_ETHER_LOOPBACK_TEST +extern void eth_loopback_test(void); +#endif /* CONFIG_ETHER_LOOPBACK_TEST */ + +extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + #include "clkinit.h" #include "ioconfig.h" /* I/O configuration table */ @@ -152,18 +159,18 @@ int checkboard(void) /* ------------------------------------------------------------------------- */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; volatile uchar c = 0; - volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8); - uint psdmr = CFG_PSDMR; + volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8); + uint psdmr = CONFIG_SYS_PSDMR; int i; uint psrt = 14; /* for no SPD */ uint chipselects = 1; /* for no SPD */ - uint sdram_size = CFG_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */ - uint or = CFG_OR2_PRELIM; /* for no SPD */ + uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */ + uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */ #ifdef SDRAM_SPD_ADDR uint data_width; uint rows; @@ -243,15 +250,15 @@ long int initdram(int board_type) /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ if(caslatency < 2) { - printf("CL was %d, forcing to 2\n", caslatency); + printf("WARNING: CL was %d, forcing to 2\n", caslatency); caslatency = 2; } if(rows > 14) { - printf("This doesn't look good, rows = %d, should be <= 14\n", rows); + printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", rows); rows = 14; } if(cols > 11) { - printf("This doesn't look good, columns = %d, should be <= 11\n", cols); + printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", cols); cols = 11; } @@ -376,10 +383,10 @@ long int initdram(int board_type) * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; memctl->memc_psrt = psrt; memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; @@ -402,7 +409,7 @@ long int initdram(int board_type) if(chipselects > 1) { ramaddr += sdram_size; - memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size; memctl->memc_or3 = or; memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; @@ -439,8 +446,8 @@ int misc_init_r(void) /* * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization. */ - volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */); - volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT); + volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */); + volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); int reg; /* I2C register value */ char *ep; /* Environment pointer */ @@ -450,6 +457,15 @@ int misc_init_r(void) int sample_128x; /* Use 128/4 clocking for the ADC/DAC */ int right_just; /* Is the data to the DAC right justified? */ int mclk_divide; /* MCLK Divide */ + int quiet; /* Quiet or minimal output mode */ + + quiet = 0; + if ((ep = getenv("quiet")) != NULL) { + quiet = simple_strtol(ep, NULL, 10); + } + else { + setenv("quiet", "0"); + } /* * SACSng custom initialization: @@ -517,8 +533,12 @@ int misc_init_r(void) setenv("Daq128xSampling", "1"); } - /* Display the ADC/DAC clocking information */ - Daq_Display_Clocks(); + /* + * Display the ADC/DAC clocking information + */ + if (!quiet) { + Daq_Display_Clocks(); + } /* * Determine the DAC data justification @@ -553,7 +573,9 @@ int misc_init_r(void) * 4) Enable address matching by setting the MSB in register 7 */ - printf("Initializing the ADC...\n"); + if (!quiet) { + printf("Initializing the ADC...\n"); + } udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */ iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */ @@ -615,7 +637,9 @@ int misc_init_r(void) * sending an I2C "start" sequence. When we bring the I2C back to * the normal state, we send an I2C "stop" sequence. */ - printf("Initializing the DAC...\n"); + if (!quiet) { + printf("Initializing the DAC...\n"); + } /* * Bring the I2C clock and data lines low for initialization @@ -695,7 +719,16 @@ int misc_init_r(void) I2C_DELAY; I2C_TRISTATE; - printf("\n"); + if (!quiet) { + printf("\n"); + } + +#ifdef CONFIG_ETHER_LOOPBACK_TEST + /* + * Run the Ethernet loopback test + */ + eth_loopback_test (); +#endif /* CONFIG_ETHER_LOOPBACK_TEST */ #ifdef CONFIG_SHOW_BOOT_PROGRESS /* @@ -758,17 +791,44 @@ static int last_boot_progress; void show_boot_progress (int status) { - if(status != -1) { + int i,j; + if(status > 0) { last_boot_progress = status; } else { /* - * Houston, we have a problem. Blink the last OK status which - * indicates where things failed. + * If a specific failure code is given, flash this code + * else just use the last success code we've seen */ - status_led_set(STATUS_LED_RED, STATUS_LED_ON); - flash_code(last_boot_progress, 5, 3); - udelay(1000000); - status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING); + if(status < -1) + last_boot_progress = -status; + + /* + * Flash this code 5 times + */ + for(j=0; j<5; j++) { + /* + * Houston, we have a problem. + * Blink the last OK status which indicates where things failed. + */ + status_led_set(STATUS_LED_RED, STATUS_LED_ON); + flash_code(last_boot_progress, 5, 3); + + /* + * Delay 5 seconds between repetitions, + * with the fault LED blinking + */ + for(i=0; i<5; i++) { + status_led_set(STATUS_LED_RED, STATUS_LED_OFF); + udelay(500000); + status_led_set(STATUS_LED_RED, STATUS_LED_ON); + udelay(500000); + } + } + + /* + * Reset the board to retry initialization. + */ + do_reset (NULL, 0, 0, NULL); } } #endif /* CONFIG_SHOW_BOOT_PROGRESS */ @@ -777,42 +837,35 @@ void show_boot_progress (int status) /* * The following are used to control the SPI chip selects for the SPI command. */ -#if (CONFIG_COMMANDS & CFG_CMD_SPI) +#if defined(CONFIG_CMD_SPI) #define SPI_ADC_CS_MASK 0x00000800 #define SPI_DAC_CS_MASK 0x00001000 -void spi_adc_chipsel(int cs) -{ - volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */); +static const u32 cs_mask[] = { + SPI_ADC_CS_MASK, + SPI_DAC_CS_MASK, +}; - if(cs) - iopd->pdat &= ~SPI_ADC_CS_MASK; /* activate the chip select */ - else - iopd->pdat |= SPI_ADC_CS_MASK; /* deactivate the chip select */ +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]); } -void spi_dac_chipsel(int cs) +void spi_cs_activate(struct spi_slave *slave) { - volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */); + volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */); - if(cs) - iopd->pdat &= ~SPI_DAC_CS_MASK; /* activate the chip select */ - else - iopd->pdat |= SPI_DAC_CS_MASK; /* deactivate the chip select */ + iopd->pdat &= ~cs_mask[slave->cs]; } -/* - * The SPI command uses this table of functions for controlling the SPI - * chip selects: it calls the appropriate function to control the SPI - * chip selects. - */ -spi_chipsel_type spi_chipsel[] = { - spi_adc_chipsel, - spi_dac_chipsel -}; -int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); +void spi_cs_deactivate(struct spi_slave *slave) +{ + volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */); -#endif /* CFG_CMD_SPI */ + iopd->pdat |= cs_mask[slave->cs]; +} + +#endif #endif /* CONFIG_MISC_INIT_R */