X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fsamsung%2Funiversal_c210%2Funiversal.c;h=9b2770f9d117ad44ec8c5d1907127c4fdeae5315;hb=57966101c827fcfa215aedee59f0e5aa558b7604;hp=7a4941c0521dce0409ca37cb3da7ab32268215f9;hpb=ea7991b8f14f258713e8a8ac89cdc6739d487383;p=u-boot diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 7a4941c052..9b2770f9d1 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -23,15 +23,21 @@ */ #include +#include +#include #include +#include #include #include #include #include -#include +#include +#include +#include +#include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -49,22 +55,17 @@ static int get_hwrev(void) return board_rev & 0xFF; } -static void check_hw_revision(void); +static void init_pmic_lcd(void); -int board_init(void) +int power_init_board(void) { - gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; - gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; + int ret; - gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + ret = pmic_init(I2C_5); + if (ret) + return ret; -#if defined(CONFIG_PMIC) - pmic_init(); -#endif - - check_hw_revision(); - printf("HW Revision:\t0x%x\n", board_rev); + init_pmic_lcd(); return 0; } @@ -113,7 +114,9 @@ static unsigned short get_adc_value(int channel) static int adc_power_control(int on) { int ret; - struct pmic *p = get_pmic(); + struct pmic *p = pmic_get("MAX8998_PMIC"); + if (!p) + return -ENODEV; if (pmic_probe(p)) return -1; @@ -236,7 +239,9 @@ int board_mmc_init(bd_t *bis) static int s5pc210_phy_control(int on) { int ret = 0; - struct pmic *p = get_pmic(); + struct pmic *p = pmic_get("MAX8998_PMIC"); + if (!p) + return -ENODEV; if (pmic_probe(p)) return -1; @@ -276,3 +281,245 @@ struct s3c_plat_otg_data s5pc210_otg_data = { .usb_flags = PHY0_SLEEP, }; #endif + +int board_early_init_f(void) +{ + wdt_stop(); + + return 0; +} + +#ifdef CONFIG_SOFT_SPI +static void soft_spi_init(void) +{ + gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK, + CONFIG_SOFT_SPI_MODE & SPI_CPOL); + gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1); + gpio_direction_input(CONFIG_SOFT_SPI_GPIO_MISO); + gpio_direction_output(CONFIG_SOFT_SPI_GPIO_CS, + !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH)); +} + +void spi_cs_activate(struct spi_slave *slave) +{ + gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS, + !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH)); + SPI_SCL(1); + gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS, + CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS, + !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH)); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void universal_spi_scl(int bit) +{ + gpio_set_value(CONFIG_SOFT_SPI_GPIO_SCLK, bit); +} + +void universal_spi_sda(int bit) +{ + gpio_set_value(CONFIG_SOFT_SPI_GPIO_MOSI, bit); +} + +int universal_spi_read(void) +{ + return gpio_get_value(CONFIG_SOFT_SPI_GPIO_MISO); +} +#endif + +static void init_pmic_lcd(void) +{ + unsigned char val; + int ret = 0; + + struct pmic *p = pmic_get("MAX8998_PMIC"); + + if (!p) + return; + + if (pmic_probe(p)) + return; + + /* LDO7 1.8V */ + val = 0x02; /* (1800 - 1600) / 100; */ + ret |= pmic_reg_write(p, MAX8998_REG_LDO7, val); + + /* LDO17 3.0V */ + val = 0xe; /* (3000 - 1600) / 100; */ + ret |= pmic_reg_write(p, MAX8998_REG_LDO17, val); + + /* Disable unneeded regulators */ + /* + * ONOFF1 + * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON + * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON + */ + val = 0xB9; + ret |= pmic_reg_write(p, MAX8998_REG_ONOFF1, val); + + /* ONOFF2 + * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON, + * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF + */ + val = 0x50; + ret |= pmic_reg_write(p, MAX8998_REG_ONOFF2, val); + + /* ONOFF3 + * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF + * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF + */ + val = 0x00; + ret |= pmic_reg_write(p, MAX8998_REG_ONOFF3, val); + + if (ret) + puts("LCD pmic initialisation error!\n"); +} + +void exynos_cfg_lcd_gpio(void) +{ + unsigned int i, f3_end = 4; + + for (i = 0; i < 8; i++) { + /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */ + s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2)); + /* pull-up/down disable */ + s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE); + + /* drive strength to max (24bit) */ + s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X); + s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW); + s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X); + s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW); + s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X); + s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW); + } + + for (i = 0; i < f3_end; i++) { + /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */ + s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2)); + /* pull-up/down disable */ + s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE); + /* drive strength to max (24bit) */ + s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X); + s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW); + } + + /* gpio pad configuration for LCD reset. */ + s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT); + + spi_init(); +} + +void exynos_reset_lcd(void) +{ + s5p_gpio_set_value(&gpio2->y4, 5, 1); + udelay(10000); + s5p_gpio_set_value(&gpio2->y4, 5, 0); + udelay(10000); + s5p_gpio_set_value(&gpio2->y4, 5, 1); + udelay(100); +} + +void exynos_lcd_power_on(void) +{ + struct pmic *p = pmic_get("MAX8998_PMIC"); + + if (!p) + return; + + if (pmic_probe(p)) + return; + + pmic_set_output(p, MAX8998_REG_ONOFF3, MAX8998_LDO17, LDO_ON); + pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON); +} + +vidinfo_t panel_info = { + .vl_freq = 60, + .vl_col = 480, + .vl_row = 800, + .vl_width = 480, + .vl_height = 800, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_hsp = CONFIG_SYS_HIGH, + .vl_vsp = CONFIG_SYS_HIGH, + .vl_dp = CONFIG_SYS_HIGH, + + .vl_bpix = 5, /* Bits per pixel */ + + /* LD9040 LCD Panel */ + .vl_hspw = 2, + .vl_hbpd = 16, + .vl_hfpd = 16, + + .vl_vspw = 2, + .vl_vbpd = 8, + .vl_vfpd = 8, + .vl_cmd_allow_len = 0xf, + + .win_id = 0, + .dual_lcd_enabled = 0, + + .init_delay = 0, + .power_on_delay = 10000, + .reset_delay = 10000, + .interface_mode = FIMD_RGB_INTERFACE, + .mipi_enabled = 0, +}; + +void exynos_cfg_ldo(void) +{ + ld9040_cfg_ldo(); +} + +void exynos_enable_ldo(unsigned int onoff) +{ + ld9040_enable_ldo(onoff); +} + +void init_panel_info(vidinfo_t *vid) +{ + vid->logo_on = 1; + vid->resolution = HD_RESOLUTION; + vid->rgb_mode = MODE_RGB_P; + +#ifdef CONFIG_TIZEN + get_tizen_logo_info(vid); +#endif + + /* for LD9040. */ + vid->pclk_name = 1; /* MPLL */ + vid->sclk_div = 1; + + setenv("lcdinfo", "lcd=ld9040"); +} + +int board_init(void) +{ + gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; + gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; + + gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + +#ifdef CONFIG_SOFT_SPI + soft_spi_init(); +#endif + check_hw_revision(); + printf("HW Revision:\t0x%x\n", board_rev); + + return 0; +}