X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fsandburst%2Fkaref%2Fkaref.c;h=92b15aa50fba70b3077a980a722e77f5e16d72db;hb=25ae8aeb54a6ca89ba1fd11c00865b8fed9348b4;hp=72ce976350e47b23e8fe0b2b9f236a762a608e53;hpb=1c7015100a620582224f25eb057573a0fe147648;p=u-boot diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c index 72ce976350..92b15aa50f 100644 --- a/board/sandburst/karef/karef.c +++ b/board/sandburst/karef/karef.c @@ -26,12 +26,17 @@ #include #include "karef.h" #include "karef_version.h" +#include #include #include #include #include #include "../common/sb_common.h" #include "../common/ppc440gx_i2c.h" +#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \ + defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) +#include +#endif void fpga_init (void); @@ -62,10 +67,10 @@ int board_early_init_f (void) ppc440_gpio_regs_t *gpio_regs; /* Enable GPIO interrupts */ - mtsdr(sdr_pfc0, 0x00103E00); + mtsdr(SDR0_PFC0, 0x00103E00); /* Setup access for LEDs, and system topology info */ - gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; @@ -75,7 +80,7 @@ int board_early_init_f (void) /*--------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------*/ - mtebc(xbcfg, + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | @@ -85,7 +90,7 @@ int board_early_init_f (void) /*--------------------------------------------------------------------+ | 1/2 MB FLASH. Initialize bank 0 with default values. +-------------------------------------------------------------------*/ - mtebc(pb0ap, + mtebc(PB0AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -93,12 +98,12 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | + mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*--------------------------------------------------------------------+ | 8KB NVRAM/RTC. Initialize bank 1 with default values. +-------------------------------------------------------------------*/ - mtebc(pb1ap, + mtebc(PB1AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -106,13 +111,13 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) | + mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*--------------------------------------------------------------------+ | Compact Flash, uses 2 Chip Selects (2 & 6) +-------------------------------------------------------------------*/ - mtebc(pb2ap, + mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -120,40 +125,40 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) | + mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); /*--------------------------------------------------------------------+ | KaRef Scan FPGA. Initialize bank 3 with default values. +-------------------------------------------------------------------*/ - mtebc(pb5ap, + mtebc(PB5AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) | + mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48200000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ | MAC A & B for Kamino. OFEM FPGA decodes the addresses | Initialize bank 4 with default values. +-------------------------------------------------------------------*/ - mtebc(pb4ap, + mtebc(PB4AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) | + mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) | EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ | OFEM FPGA Initialize bank 5 with default values. +-------------------------------------------------------------------*/ - mtebc(pb3ap, + mtebc(PB3AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | @@ -161,14 +166,14 @@ int board_early_init_f (void) EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) | + mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48400000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ | Compact Flash, uses 2 Chip Selects (2 & 6) +-------------------------------------------------------------------*/ - mtebc(pb6ap, + mtebc(PB6AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -176,20 +181,20 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) | + mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); /*--------------------------------------------------------------------+ | BME-32. Initialize bank 7 with default values. +-------------------------------------------------------------------*/ - mtebc(pb7ap, + mtebc(PB7AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) | + mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ @@ -207,36 +212,36 @@ int board_early_init_f (void) * UIC2 UIC1 * UIC3 UIC2 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non- critical */ - mtdcr (uic1pr, 0xfffffe03); /* polarity */ - mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ - - mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uic2er, 0x00000000); /* disable all */ - mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffc8ff); /* polarity */ - mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */ - mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic2sr, 0xffffffff); /* clear all */ - - mtdcr (uic3sr, 0xffffffff); /* clear all */ - mtdcr (uic3er, 0x00000000); /* disable all */ - mtdcr (uic3cr, 0x00000000); /* all non-critical */ - mtdcr (uic3pr, 0xffff83ff); /* polarity */ - mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */ - mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic3sr, 0xffffffff); /* clear all */ - - mtdcr (uic0sr, 0xfc000000); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000000); /* all non-critical */ - mtdcr (uic0pr, 0xfc000000); - mtdcr (uic0tr, 0x00000000); - mtdcr (uic0vr, 0x00000001); + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + mtdcr (UIC1ER, 0x00000000); /* disable all */ + mtdcr (UIC1CR, 0x00000000); /* all non- critical */ + mtdcr (UIC1PR, 0xfffffe03); /* polarity */ + mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */ + mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC1SR, 0xffffffff); /* clear all */ + + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + mtdcr (UIC2ER, 0x00000000); /* disable all */ + mtdcr (UIC2CR, 0x00000000); /* all non-critical */ + mtdcr (UIC2PR, 0xffffc8ff); /* polarity */ + mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */ + mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC2SR, 0xffffffff); /* clear all */ + + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + mtdcr (UIC3ER, 0x00000000); /* disable all */ + mtdcr (UIC3CR, 0x00000000); /* all non-critical */ + mtdcr (UIC3PR, 0xffff83ff); /* polarity */ + mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (UIC3SR, 0xffffffff); /* clear all */ + + mtdcr (UIC0SR, 0xfc000000); /* clear all */ + mtdcr (UIC0ER, 0x00000000); /* disable all */ + mtdcr (UIC0CR, 0x00000000); /* all non-critical */ + mtdcr (UIC0PR, 0xfc000000); + mtdcr (UIC0TR, 0x00000000); + mtdcr (UIC0VR, 0x00000001); fpga_init(); @@ -259,8 +264,8 @@ int checkboard (void) KAREF_FPGA_REGS_ST *karef_ps; OFEM_FPGA_REGS_ST *ofem_ps; - karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; - ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; + ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; scan_id = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK) @@ -299,7 +304,7 @@ int checkboard (void) "Serial Number: %d\n", sernum); printf ("%s\n", KAREF_U_BOOT_REL_STR); - printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER); + printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); if (sbcommon_get_master()) { printf("Slot 0 - Master\nSlave board"); if (sbcommon_secondary_present()) @@ -319,7 +324,7 @@ int checkboard (void) /* Fix the ack in the bme 32 */ udelay(5000); - out32(CFG_BME32_BASE + 0x0000000C, 0x00000001); + out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001); asm("eieio"); @@ -335,7 +340,7 @@ int misc_init_f (void) { /* Turn on i2c bus 1 */ puts ("I2C1: "); - i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); puts ("ready\n"); /* Turn on fans 3 & 4 */ @@ -353,6 +358,7 @@ int misc_init_r (void) { unsigned short sernum; char envstr[255]; + uchar enetaddr[6]; KAREF_FPGA_REGS_ST *karef_ps; OFEM_FPGA_REGS_ST *ofem_ps; @@ -366,7 +372,8 @@ int misc_init_r (void) setenv("ubrelver", KAREF_U_BOOT_REL_STR); memset(envstr, 0, 255); - sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER); + sprintf (envstr, "Built %s %s by %s", + U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); setenv("bldstr", envstr); saveenv(); @@ -397,8 +404,8 @@ int misc_init_r (void) } if( getenv("fakeled")) { - karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; - ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; + ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK; karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK; setenv("bootdelay", "-1"); @@ -406,6 +413,34 @@ int misc_init_r (void) printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); } +#ifdef CONFIG_HAS_ETH0 + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { + board_get_enetaddr(0, enetaddr); + eth_setenv_enetaddr("ethaddr", enetaddr); + } +#endif + +#ifdef CONFIG_HAS_ETH1 + if (!eth_getenv_enetaddr("eth1addr", enetaddr)) { + board_get_enetaddr(1, enetaddr); + eth_setenv_enetaddr("eth1addr", enetaddr); + } +#endif + +#ifdef CONFIG_HAS_ETH2 + if (!eth_getenv_enetaddr("eth2addr", enetaddr)) { + board_get_enetaddr(2, enetaddr); + eth_setenv_enetaddr("eth2addr", enetaddr); + } +#endif + +#ifdef CONFIG_HAS_ETH3 + if (!eth_getenv_enetaddr("eth3addr", enetaddr)) { + board_get_enetaddr(3, enetaddr); + eth_setenv_enetaddr("eth3addr", enetaddr); + } +#endif + return (0); } @@ -417,7 +452,7 @@ void ide_set_reset(int on) { KAREF_FPGA_REGS_ST *karef_ps; /* TODO: ide reset */ - karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; if (on) { karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; @@ -440,7 +475,7 @@ void fpga_init(void) /* Ensure we have power all around */ udelay(500); - karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; tmp = SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK | SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK | @@ -470,7 +505,7 @@ void fpga_init(void) SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK | SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK; - ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; ofem_ps->reset_ul = tmp; ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT; @@ -576,7 +611,7 @@ int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(kasetup, 1, 1, karefSetupVars, - "kasetup - Set environment to factory defaults\n", NULL); + "Set environment to factory defaults", ""); U_BOOT_CMD(karecover, 1, 1, karefRecover, - "karecover - Set environment to allow for fs recovery\n", NULL); + "Set environment to allow for fs recovery", "");