X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fsbc8349%2Fpci.c;h=ac5f30b46e9da375b8c85ddd941400029bd479c3;hb=9d4fc99dbdbfda1260aad478e83fca7cdf0e1a32;hp=eadf230983dc41dd5d655ac026995c7d69017643;hpb=37896293bc991bddb75ccac887b54e9a61f36320;p=u-boot diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c index eadf230983..ac5f30b46e 100644 --- a/board/sbc8349/pci.c +++ b/board/sbc8349/pci.c @@ -30,14 +30,18 @@ #include #include #include +#if defined(CONFIG_OF_LIBFDT) +#include +#include +#endif DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_PCI /* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE #ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc8349emds_config_table[] = { @@ -86,7 +90,7 @@ pci_init_board(void) u32 dev; struct pci_controller * hose; - immr = (immap_t *)CFG_IMMR; + immr = (immap_t *)CONFIG_SYS_IMMR; clk = (clk83xx_t *)&immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; @@ -128,10 +132,10 @@ pci_init_board(void) /* * Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; /* @@ -139,18 +143,18 @@ pci_init_board(void) */ /* PCI1 mem space - prefetch */ - pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); /* PCI1 IO space */ - pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); /* PCI1 mmio - non-prefetch mem space */ - pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); /* @@ -169,23 +173,23 @@ pci_init_board(void) /* PCI memory prefetch space */ pci_set_region(hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM|PCI_REGION_PREFETCH); /* PCI memory space */ pci_set_region(hose->regions + 1, - CFG_PCI1_MMIO_BASE, - CFG_PCI1_MMIO_PHYS, - CFG_PCI1_MMIO_SIZE, + CONFIG_SYS_PCI1_MMIO_BASE, + CONFIG_SYS_PCI1_MMIO_PHYS, + CONFIG_SYS_PCI1_MMIO_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); /* System memory space */ @@ -193,13 +197,13 @@ pci_init_board(void) CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, gd->ram_size, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; pci_setup_indirect(hose, - (CFG_IMMR+0x8300), - (CFG_IMMR+0x8304)); + (CONFIG_SYS_IMMR+0x8300), + (CONFIG_SYS_IMMR+0x8304)); pci_register_hose(hose); @@ -235,18 +239,18 @@ pci_init_board(void) */ /* PCI2 mem space - prefetch */ - pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); /* PCI2 IO space */ - pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); /* PCI2 mmio - non-prefetch mem space */ - pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); /* @@ -265,23 +269,23 @@ pci_init_board(void) /* PCI memory prefetch space */ pci_set_region(hose->regions + 0, - CFG_PCI2_MEM_BASE, - CFG_PCI2_MEM_PHYS, - CFG_PCI2_MEM_SIZE, + CONFIG_SYS_PCI2_MEM_BASE, + CONFIG_SYS_PCI2_MEM_PHYS, + CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM|PCI_REGION_PREFETCH); /* PCI memory space */ pci_set_region(hose->regions + 1, - CFG_PCI2_MMIO_BASE, - CFG_PCI2_MMIO_PHYS, - CFG_PCI2_MMIO_SIZE, + CONFIG_SYS_PCI2_MMIO_BASE, + CONFIG_SYS_PCI2_MMIO_PHYS, + CONFIG_SYS_PCI2_MMIO_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 2, - CFG_PCI2_IO_BASE, - CFG_PCI2_IO_PHYS, - CFG_PCI2_IO_SIZE, + CONFIG_SYS_PCI2_IO_BASE, + CONFIG_SYS_PCI2_IO_PHYS, + CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); /* System memory space */ @@ -289,13 +293,13 @@ pci_init_board(void) CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, gd->ram_size, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; pci_setup_indirect(hose, - (CFG_IMMR+0x8380), - (CFG_IMMR+0x8384)); + (CONFIG_SYS_IMMR+0x8380), + (CONFIG_SYS_IMMR+0x8384)); pci_register_hose(hose); @@ -323,26 +327,40 @@ pci_init_board(void) } -#ifdef CONFIG_OF_FLAT_TREE -void -ft_pci_setup(void *blob, bd_t *bd) +#if defined(CONFIG_OF_LIBFDT) +void ft_pci_setup(void *blob, bd_t *bd) { - u32 *p; - int len; - - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); - if (p != NULL) { - p[0] = pci_hose[0].first_busno; - p[1] = pci_hose[0].last_busno; + int nodeoffset; + int tmp[2]; + const char *path; + + nodeoffset = fdt_path_offset(blob, "/aliases"); + if (nodeoffset >= 0) { + path = fdt_getprop(blob, nodeoffset, "pci0", NULL); + if (path) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + + tmp[0] = cpu_to_be32(gd->pci_clk); + do_fixup_by_path(blob, path, "clock-frequency", + &tmp, sizeof(tmp[0]), 1); } - #ifdef CONFIG_MPC83XX_PCI2 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); - if (p != NULL) { - p[0] = pci_hose[1].first_busno; - p[1] = pci_hose[1].last_busno; - } + path = fdt_getprop(blob, nodeoffset, "pci1", NULL); + if (path) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + + tmp[0] = cpu_to_be32(gd->pci_clk); + do_fixup_by_path(blob, path, "clock-frequency", + &tmp, sizeof(tmp[0]), 1); + } #endif + } } -#endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_OF_LIBFDT */ #endif /* CONFIG_PCI */