X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fsbc8349%2Fsbc8349.c;h=42f4c1ef06774506a204641e6869c689dbcb4173;hb=721d0b0026971924605701a0e409ded91e093caa;hp=34861d4e15793220406719d941bbc56329f56429;hpb=0f898604945af4543c1525fc33b6bae621a3b805;p=u-boot diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 34861d4e15..42f4c1ef06 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -89,26 +89,25 @@ phys_size_t initdram (int board_type) int fixed_sdram(void) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size>>1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } + u32 msize = CONFIG_SYS_DDR_SIZE; + u32 ddr_size = msize << 20; /* DDR size in bytes */ + u32 ddr_size_log2 = __ilog2(msize); + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); #if (CONFIG_SYS_DDR_SIZE != 256) #warning Currently any ddr size other than 256 is not supported #endif - im->ddr.csbnds[2].csbnds = 0x0000000f; - im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG; + +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[2].csbnds = + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; /* currently we use only one CS, so disable the other banks */ im->ddr.cs_config[0] = 0; @@ -160,7 +159,7 @@ int checkboard (void) void sdram_init(void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbc = &immap->lbus; + volatile fsl_lbc_t *lbc = &immap->im_lbc; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; puts("\n SDRAM on Local Bus: ");