X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fsbc8548%2Fsbc8548.c;h=d584276253a5e33414a085d2e5414844cfd11a94;hb=365475e6d14bc1ea9d218c0fd1fe96878a9db94e;hp=d1ef3bee50f9bc146b0758ada32ec7d2cf01487f;hpb=2a6b3b74d85cff3f9a76edd09a7b2e8e25bb4eb4;p=u-boot

diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index d1ef3bee50..d584276253 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -7,23 +7,7 @@
  *
  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -31,7 +15,7 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/fsl_serdes.h>
 #include <spd_sdram.h>
 #include <netdev.h>
@@ -76,11 +60,15 @@ local_bus_init(void)
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
-	uint clkdiv;
+	uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
 	sys_info_t sysinfo;
 
 	get_sys_info(&sysinfo);
-	clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
+
+	lbc_mhz = sysinfo.freq_localbus / 1000000;
+	clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
+
+	debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
 
 	out_be32(&gur->lbiuiplldcr1, 0x00078080);
 	if (clkdiv == 16) {
@@ -91,10 +79,38 @@ local_bus_init(void)
 		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
 	}
 
-	setbits_be32(&lbc->lcrr, 0x00030000);
+	/*
+	 * Local Bus Clock > 83.3 MHz. According to timing
+	 * specifications set LCRR[EADC] to 2 delay cycles.
+	 */
+	if (lbc_mhz > 83) {
+		lcrr &= ~LCRR_EADC;
+		lcrr |= LCRR_EADC_2;
+	}
 
+	/*
+	 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
+	 * disable PLL bypass for Local Bus Clock > 83 MHz.
+	 */
+	if (lbc_mhz >= 66)
+		lcrr &= (~LCRR_DBYP);	/* DLL Enabled */
+
+	else
+		lcrr |= LCRR_DBYP;	/* DLL Bypass */
+
+	out_be32(&lbc->lcrr, lcrr);
 	asm("sync;isync;msync");
 
+	 /*
+	 * According to MPC8548ERMAD Rev.1.3 read back LCRR
+	 * and terminate with isync
+	 */
+	lcrr = in_be32(&lbc->lcrr);
+	asm ("isync;");
+
+	/* let DLL stabilize */
+	udelay(500);
+
 	out_be32(&lbc->ltesr, 0xffffffff);	/* Clear LBC error IRQs */
 	out_be32(&lbc->lteir, 0xffffffff);	/* Enable LBC error IRQs */
 }