X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fsbc8548%2Ftlb.c;h=2f7e4c536488150529f660fef1943ff44324f67a;hb=5f98d0b5d3038cb3345712bc779efacaba4322f7;hp=38bdeb37c3009bcdc44d65ec6dc8ea95e8621d45;hpb=589a100620ef793390d4a3bde7012430353f3ae3;p=u-boot

diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index 38bdeb37c3..2f7e4c5364 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -4,23 +4,7 @@
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -46,12 +30,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 	/*
 	 * TLB 0:	64M	Non-cacheable, guarded
-	 * 0xfc000000	56M	8MB -> 64MB of user flash
+	 * 0xfc000000	56M	unused
 	 * 0xff800000	8M	boot FLASH
+	 *	.... or ....
+	 * 0xfc000000	64M	user flash
+	 *
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000,
-		      CONFIG_SYS_ALT_FLASH + 0x800000,
+	SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_64M, 1),
 
@@ -65,44 +51,36 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      0, 1, BOOKE_PAGESZ_1G, 1),
 
 	/*
-	 * TLB 2:	256M Cacheable, non-guarded
-	 * 0x0		256M DDR SDRAM
-	 */
-#if !defined(CONFIG_SPD_EEPROM)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-#endif
-
-	/*
-	 * TLB 3:	64M	Non-cacheable, guarded
+	 * TLB 2:	64M	Non-cacheable, guarded
 	 * 0xe0000000	1M	CCSRBAR
 	 * 0xe2000000	8M	PCI1 IO
 	 * 0xe2800000	8M	PCIe IO
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_64M, 1),
+		      0, 2, BOOKE_PAGESZ_64M, 1),
 
+#ifdef CONFIG_SYS_LBC_SDRAM_BASE
 	/*
-	 * TLB 4:	64M	Cacheable, non-guarded
+	 * TLB 3:	64M	Cacheable, non-guarded
 	 * 0xf0000000	64M	LBC SDRAM First half
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 4, BOOKE_PAGESZ_64M, 1),
+		      0, 3, BOOKE_PAGESZ_64M, 1),
 
 	/*
-	 * TLB 5:	64M	Cacheable, non-guarded
+	 * TLB 4:	64M	Cacheable, non-guarded
 	 * 0xf4000000	64M	LBC SDRAM Second half
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
 		      CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 5, BOOKE_PAGESZ_64M, 1),
+		      0, 4, BOOKE_PAGESZ_64M, 1),
+#endif
 
 	/*
-	 * TLB 6:	16M	Cacheable, non-guarded
+	 * TLB 5:	16M	Cacheable, non-guarded
 	 * 0xf8000000	1M	7-segment LED display
 	 * 0xf8100000	1M	User switches
 	 * 0xf8300000	1M	Board revision
@@ -110,24 +88,34 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_16M, 1),
+		      0, 5, BOOKE_PAGESZ_16M, 1),
 
+#ifndef CONFIG_SYS_ALT_BOOT
 	/*
-	 * TLB 7:	4M	Non-cacheable, guarded
-	 * 0xfb800000	4M	1st 4MB block of 64MB user FLASH
+	 * TLB 6:	64M	Non-cacheable, guarded
+	 * 0xec000000	64M	64MB user FLASH
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_4M, 1),
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+#else
+	/*
+	 * TLB 6:	4M	Non-cacheable, guarded
+	 * 0xef800000	4M	1st 1/2 8MB soldered FLASH
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_4M, 1),
 
 	/*
-	 * TLB 8:	4M	Non-cacheable, guarded
-	 * 0xfbc00000	4M	2nd 4MB block of 64MB user FLASH
+	 * TLB 7:	4M	Non-cacheable, guarded
+	 * 0xefc00000	4M	2nd half 8MB soldered FLASH
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
 		      CONFIG_SYS_ALT_FLASH + 0x400000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 8, BOOKE_PAGESZ_4M, 1),
+		      0, 7, BOOKE_PAGESZ_4M, 1),
+#endif
 
 };