X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fsbc8560%2Ftlb.c;h=fe0ac763af21d19131617f260f12026fa786e750;hb=ec6baf53f7691da4751e98d47a014acf266ab994;hp=d073399606caf8616ac9b4f91059e12bebe8008b;hpb=234ea73c660cfd0b1c98de00995c32d4152d202f;p=u-boot

diff --git a/board/sbc8560/tlb.c b/board/sbc8560/tlb.c
index d073399606..fe0ac763af 100644
--- a/board/sbc8560/tlb.c
+++ b/board/sbc8560/tlb.c
@@ -28,7 +28,7 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 /* TLB for CCSRBAR (IMMR) */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_1M, 1),
 
@@ -44,20 +44,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
 #if !defined(CONFIG_SPD_EEPROM)
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 5, BOOKE_PAGESZ_256M, 1),
 #endif
 
-	SET_TLB_ENTRY(1, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 6, BOOKE_PAGESZ_16K, 1),
 
-	SET_TLB_ENTRY(1, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_256M, 1),
 };