X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fsbc8641d%2Fsbc8641d.c;h=5c30b2676e4d573b13ea047c27a95a0e04520ef5;hb=e1ccf97c5d7651664d37c0c5aa243874b8851b2d;hp=191045a239528ed8283fcc2bee96fb76d52b687c;hpb=f8030519bbe20b836f3939742b959cbadfaad51b;p=u-boot diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 191045a239..5c30b2676e 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -33,15 +33,12 @@ #include #include #include -#include +#include #include +#include #include #include -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc (unsigned int dram_size); -#endif - long int fixed_sdram (void); int board_early_init_f (void) @@ -66,18 +63,6 @@ phys_size_t initdram (int board_type) dram_size = fixed_sdram (); #endif -#if defined(CONFIG_SYS_RAMBOOT) - puts (" DDR: "); - return dram_size; -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc (dram_size); -#endif - puts (" DDR: "); return dram_size; } @@ -138,9 +123,9 @@ long int fixed_sdram (void) ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1A; + ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A; ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2; - ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL; ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; @@ -151,7 +136,7 @@ long int fixed_sdram (void) udelay (500); - ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1B; + ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B; asm ("sync; isync"); udelay (500); @@ -169,9 +154,9 @@ long int fixed_sdram (void) ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0; ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1; ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2; - ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1A; + ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A; ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2; - ddr->sdram_mode_1 = CONFIG_SYS_DDR2_MODE_1; + ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1; ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2; ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL; ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL; @@ -182,7 +167,7 @@ long int fixed_sdram (void) udelay (500); - ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1B; + ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B; asm ("sync; isync"); udelay (500); @@ -196,155 +181,19 @@ long int fixed_sdram (void) * Initialize PCI Devices, report devices found. */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_fsl86xxads_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, - {} -}; -#endif - -static struct pci_controller pci1_hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc86xxcts_config_table -#endif -}; -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_PCI2 -static struct pci_controller pci2_hose; -#endif /* CONFIG_PCI2 */ - -int first_free_busno = 0; - -extern int fsl_pci_setup_inbound_windows(struct pci_region *r); -extern void fsl_pci_init(struct pci_controller *hose); - void pci_init_board(void) { - volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) - >> MPC8641_PORDEVSR_IO_SEL_SHIFT; - -#ifdef CONFIG_PCI1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; -#ifdef DEBUG - uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) - >> MPC8641_PORBMSR_HA_SHIFT; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); -#endif - if ((io_sel == 2 || io_sel == 3 || io_sel == 5 - || io_sel == 6 || io_sel == 7 || io_sel == 0xF) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); - debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - debug("\n"); - - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - - fsl_pci_init(hose); - - first_free_busno=hose->last_busno+1; - printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); - - } else { - puts("PCI-EXPRESS 1: Disabled\n"); - } -} -#else - puts("PCI-EXPRESS1: Disabled\n"); -#endif /* CONFIG_PCI1 */ - -#ifdef CONFIG_PCI2 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; - struct pci_controller *hose = &pci2_hose; - struct pci_region *r = hose->regions; - - - /* inbound */ - r += fsl_pci_setup_inbound_windows(r); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI2_MEM_BASE, - CONFIG_SYS_PCI2_MEM_PHYS, - CONFIG_SYS_PCI2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI2_IO_BASE, - CONFIG_SYS_PCI2_IO_PHYS, - CONFIG_SYS_PCI2_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); - - fsl_pci_init(hose); - - first_free_busno=hose->last_busno+1; - printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); -} -#else - puts("PCI-EXPRESS 2: Disabled\n"); -#endif /* CONFIG_PCI2 */ - + fsl_pcie_init_board(0); } +#endif /* CONFIG_PCI */ #if defined(CONFIG_OF_BOARD_SETUP) -extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, - struct pci_controller *hose); - void ft_board_setup (void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI1 - ft_fsl_pci_setup(blob, "pci0", &pci1_hose); -#endif -#ifdef CONFIG_PCI2 - ft_fsl_pci_setup(blob, "pci1", &pci2_hose); -#endif + FT_FSL_PCI_SETUP; } #endif @@ -395,3 +244,41 @@ unsigned long get_board_sys_clk (ulong dummy) return val; } + +void board_reset(void) +{ +#ifdef CONFIG_SYS_RESET_ADDRESS + ulong addr = CONFIG_SYS_RESET_ADDRESS; + + /* flush and disable I/D cache */ + __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); + __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); + __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); + __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("mtspr 1008, 4"); + __asm__ __volatile__ ("isync"); + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("mtspr 1008, 5"); + __asm__ __volatile__ ("isync"); + __asm__ __volatile__ ("sync"); + + /* + * SRR0 has system reset vector, SRR1 has default MSR value + * rfi restores MSR from SRR1 and sets the PC to the SRR0 value + */ + __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); + __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); + __asm__ __volatile__ ("mtspr 27, 4"); + __asm__ __volatile__ ("rfi"); +#endif +} + +#ifdef CONFIG_MP +extern void cpu_mp_lmb_reserve(struct lmb *lmb); + +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif