X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fsbc8641d%2Fsbc8641d.c;h=c724effa06357f43137eea9cabeb8201e4c45901;hb=dedec4cfc88eeadac616d558f6104cbe2e0d46aa;hp=e7334ef576cfe5d03bcb2b716e15ada19d55c7c6;hpb=093e14c52280b4bcc84948bac605ee4d6e87b6e9;p=u-boot diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index e7334ef576..c724effa06 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include #include @@ -42,10 +42,6 @@ extern void ddr_enable_ecc (unsigned int dram_size); #endif -#if defined(CONFIG_SPD_EEPROM) -#include "spd_sdram.h" -#endif - void sdram_init (void); long int fixed_sdram (void); @@ -61,7 +57,7 @@ int checkboard (void) return 0; } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { long dram_size = 0; @@ -139,7 +135,7 @@ long int fixed_sdram (void) ddr->cs1_config = CFG_DDR_CS1_CONFIG; ddr->cs2_config = CFG_DDR_CS2_CONFIG; ddr->cs3_config = CFG_DDR_CS3_CONFIG; - ddr->ext_refrec = CFG_DDR_EXT_REFRESH; + ddr->timing_cfg_3 = CFG_DDR_TIMING_3; ddr->timing_cfg_0 = CFG_DDR_TIMING_0; ddr->timing_cfg_1 = CFG_DDR_TIMING_1; ddr->timing_cfg_2 = CFG_DDR_TIMING_2; @@ -170,7 +166,7 @@ long int fixed_sdram (void) ddr->cs1_config = CFG_DDR2_CS1_CONFIG; ddr->cs2_config = CFG_DDR2_CS2_CONFIG; ddr->cs3_config = CFG_DDR2_CS3_CONFIG; - ddr->ext_refrec = CFG_DDR2_EXT_REFRESH; + ddr->timing_cfg_3 = CFG_DDR2_EXT_REFRESH; ddr->timing_cfg_0 = CFG_DDR2_TIMING_0; ddr->timing_cfg_1 = CFG_DDR2_TIMING_1; ddr->timing_cfg_2 = CFG_DDR2_TIMING_2;