X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fsc3%2Fsc3.c;h=0216a37f63ab9de2547cd449240a8643296d6162;hb=42817eb85de1d7dec399c75dbd133ea6b5351a72;hp=5ae7b1244a7b61a0352f40573a6085d763c645fd;hpb=084f3ddac6ab624a4b1c7174b3cdf9cc25866217;p=u-boot

diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c
index 5ae7b1244a..0216a37f63 100644
--- a/board/sc3/sc3.c
+++ b/board/sc3/sc3.c
@@ -9,25 +9,7 @@
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * $Log:$
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -294,22 +276,22 @@ int board_early_init_f (void)
 
 	writeb (cpldConfig_1, CPLD_CONTROL_1);	/* disable everything in CPLD */
 
-	mtdcr (uicsr, 0xFFFFFFFF);    /* clear all ints */
-	mtdcr (uicer, 0x00000000);    /* disable all ints */
-	mtdcr (uiccr, 0x00000000);    /* set all to be non-critical */
+	mtdcr (UIC0SR, 0xFFFFFFFF);    /* clear all ints */
+	mtdcr (UIC0ER, 0x00000000);    /* disable all ints */
+	mtdcr (UIC0CR, 0x00000000);    /* set all to be non-critical */
 
 	if (IS_CAMERON) {
 		sc3_cameron_init();
 		mtdcr (0x0B6, 0x18000000);
-		mtdcr (uicpr, 0xFFFFFFF0);
-		mtdcr (uictr, 0x10001030);
+		mtdcr (UIC0PR, 0xFFFFFFF0);
+		mtdcr (UIC0TR, 0x10001030);
 	} else {
 		mtdcr (0x0B6, 0x0000000);
-		mtdcr (uicpr, 0xFFFFFFE0);
-		mtdcr (uictr, 0x10000020);
+		mtdcr (UIC0PR, 0xFFFFFFE0);
+		mtdcr (UIC0TR, 0x10000020);
 	}
-	mtdcr (uicvcr, 0x00000001);   /* set vect base=0,INT0 highest priority */
-	mtdcr (uicsr, 0xFFFFFFFF);    /* clear all ints */
+	mtdcr (UIC0VCR, 0x00000001);   /* set vect base=0,INT0 highest priority */
+	mtdcr (UIC0SR, 0xFFFFFFFF);    /* clear all ints */
 
 	/* setup other implementation specific details */
 	mtdcr (CPC0_ECR, 0x60606000);
@@ -331,16 +313,16 @@ int board_early_init_f (void)
 	}
 
 	/* Code decompression disabled */
-	mtdcr (KIAR, KCONF);
-	mtdcr (KIDR, 0x2B);
+	mtdcr (DCP0_CFGADDR, KCONF);
+	mtdcr (DCP0_CFGDATA, 0x2B);
 
 	/* CPC0_ER: enable sleep mode of (currently) unused components */
 	/* CPC0_FR: force unused components into sleep mode */
-	mtdcr (CPMER, 0x3F800000);
-	mtdcr (CPMFR, 0x14000000);
+	mtdcr (CPC0_ER, 0x3F800000);
+	mtdcr (CPC0_FR, 0x14000000);
 
 	/* set PLB priority */
-	mtdcr (0x87, 0x08000000);
+	mtdcr (PLB0_ACR, 0x08000000);
 
 	/* --------------- DMA stuff ------------------------------------- */
 	mtdcr (0x126, 0x49200000);
@@ -577,7 +559,7 @@ static int printSDRAMConfig(char reg, unsigned long cr)
 }
 
 #ifdef SC3_DEBUGOUT
-static unsigned int mbcf[] = {mem_mb0cf, mem_mb1cf, mem_mb2cf, mem_mb3cf};
+static unsigned int mbcf[] = {SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR};
 #endif
 
 phys_size_t initdram (int board_type)
@@ -591,7 +573,7 @@ phys_size_t initdram (int board_type)
 
 	puts("\nSDRAM configuration:\n");
 
-	mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
 	ul1 = mfdcr(SDRAM0_CFGDATA);
 
 	if (!(ul1 & 0x80000000)) {
@@ -604,7 +586,7 @@ phys_size_t initdram (int board_type)
 		mems += printSDRAMConfig (i, ul1);
 	}
 
-	mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
 	ul1 = mfdcr(SDRAM0_CFGDATA);
 
 	printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
@@ -614,14 +596,14 @@ phys_size_t initdram (int board_type)
 	printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
 	printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
 	puts ("Misc:\n");
-	mtdcr (SDRAM0_CFGADDR, mem_rtr);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
 	ul1 = mfdcr(SDRAM0_CFGDATA);
 	printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);
 
-	mtdcr(SDRAM0_CFGADDR,mem_pmit);
+	mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT);
 	ul2=mfdcr(SDRAM0_CFGDATA);
 
-	mtdcr(SDRAM0_CFGADDR,mem_mcopt1);
+	mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG);
 	ul1=mfdcr(SDRAM0_CFGDATA);
 
 	if (ul1 & 0x20000000)
@@ -658,7 +640,7 @@ phys_size_t initdram (int board_type)
 	else
 		puts(" -Memory lines only at write cycles active outputs\n");
 
-	mtdcr (SDRAM0_CFGADDR, mem_status);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_STATUS);
 	ul1 = mfdcr (SDRAM0_CFGDATA);
 	if (ul1 & 0x80000000)
 		puts(" -SDRAM Controller ready\n");
@@ -670,19 +652,19 @@ phys_size_t initdram (int board_type)
 
 	return (mems * 1024 * 1024);
 #else
-	mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
 	ul1 = mfdcr (SDRAM0_CFGDATA);
 	mems = printSDRAMConfig (0, ul1);
 
-	mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
 	ul1 = mfdcr (SDRAM0_CFGDATA);
 	mems += printSDRAMConfig (1, ul1);
 
-	mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
 	ul1 = mfdcr(SDRAM0_CFGDATA);
 	mems += printSDRAMConfig (2, ul1);
 
-	mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
 	ul1 = mfdcr(SDRAM0_CFGDATA);
 	mems += printSDRAMConfig (3, ul1);