X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fsocrates%2Flaw.c;h=cb55fd43d640d4a65068264aec00cdc5c70f5efa;hb=6ea4217fd0d3674e760f52762f1977e9a3408471;hp=35c4a900a9bcd70995ca7c3235dbf77a17a89512;hpb=794a5924972fc8073616e98a2668da4a5f9aea90;p=u-boot

diff --git a/board/socrates/law.c b/board/socrates/law.c
index 35c4a900a9..cb55fd43d6 100644
--- a/board/socrates/law.c
+++ b/board/socrates/law.c
@@ -36,6 +36,7 @@
  * 0x0000_0000	   0x2fff_ffff	   DDR			   512M
  * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
  * 0xc000_0000	   0xc00f_ffff	   FPGA			   1M
+ * 0xc800_0000	   0xcbff_ffff	   LIME			   64M
  * 0xe000_0000	   0xe00f_ffff	   CCSR			   1M (mapped by CCSRBAR)
  * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
  * 0xfc00_0000	   0xffff_ffff	   FLASH		   64M
@@ -46,13 +47,14 @@
  */
 
 struct law_entry law_table[] = {
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
-#if defined(CFG_FPGA_BASE)
-	SET_LAW(CFG_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+#if defined(CONFIG_SYS_FPGA_BASE)
+	SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
+	SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);