X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fsocrates%2Flaw.c;h=cb55fd43d640d4a65068264aec00cdc5c70f5efa;hb=b364727abb5aa32120f583a9611944c2444f6b41;hp=5f4b8ca4f90c375bc07e287641026cfebe25e6c7;hpb=0ad4770f8eb052a84800925ea4ab342cfc10dc32;p=u-boot diff --git a/board/socrates/law.c b/board/socrates/law.c index 5f4b8ca4f9..cb55fd43d6 100644 --- a/board/socrates/law.c +++ b/board/socrates/law.c @@ -33,13 +33,13 @@ /* * LAW(Local Access Window) configuration: * - * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x0000_0000 0x2fff_ffff DDR 512M * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xc000_0000 0xc00f_ffff FPGA 1M + * 0xc800_0000 0xcbff_ffff LIME 64M + * 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR) * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M + * 0xfc00_0000 0xffff_ffff FLASH 64M * * Notes: * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. @@ -47,11 +47,14 @@ */ struct law_entry law_table[] = { - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), +#if defined(CONFIG_SYS_FPGA_BASE) + SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#endif + SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table);