X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fspear%2Fx600%2Fx600.c;h=f8e9fddb0fb2849ac32b20c4cc40ce856ebe78c7;hb=3fef31a392a215f55044f930033f24d4e9762853;hp=96ec0ad8a5d5fd176e87f7d4d0223e8a7d2eaf9c;hpb=bd23b22badadcdc414a900828253961fc5ec6c39;p=u-boot diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c index 96ec0ad8a5..f8e9fddb0f 100644 --- a/board/spear/x600/x600.c +++ b/board/spear/x600/x600.c @@ -4,26 +4,11 @@ * * Copyright (C) 2012 Stefan Roese * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include #include @@ -83,31 +68,69 @@ void board_nand_init(void) fsmc_nand_init(nand); } -int designware_board_phy_init(struct eth_device *dev, int phy_addr, - int (*mii_write)(struct eth_device *, u8, u8, u16), - int dw_reset_phy(struct eth_device *)) +int board_phy_config(struct phy_device *phydev) { - /* Extended PHY control 1, select GMII */ - mii_write(dev, phy_addr, 23, 0x0020); - - /* Software reset necessary after GMII mode selction */ - dw_reset_phy(dev); - - /* Enable extended page register access */ - mii_write(dev, phy_addr, 31, 0x0001); - - /* 17e: Enhanced LED behavior, needs to be written twice */ - mii_write(dev, phy_addr, 17, 0x09ff); - mii_write(dev, phy_addr, 17, 0x09ff); - - /* 16e: Enhanced LED method select */ - mii_write(dev, phy_addr, 16, 0xe0ea); - - /* Disable extended page register access */ - mii_write(dev, phy_addr, 31, 0x0000); - - /* Enable clock output pin */ - mii_write(dev, phy_addr, 18, 0x0049); + unsigned short id1, id2; + + /* check whether KSZ9031 or AR8035 has to be configured */ + id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); + id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); + + if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) { + /* PHY configuration for Micrel KSZ9031 */ + printf("PHY KSZ9031 detected - "); + + phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); + + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0000); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0000); + /* tx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x0000); + /* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x03FF); + } else { + /* PHY configuration for Vitesse VSC8641 */ + printf("PHY VSC8641 detected - "); + + /* Extended PHY control 1, select GMII */ + phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); + + /* Software reset necessary after GMII mode selction */ + phy_reset(phydev); + + /* Enable extended page register access */ + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); + + /* 17e: Enhanced LED behavior, needs to be written twice */ + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); + + /* 16e: Enhanced LED method select */ + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); + + /* Disable extended page register access */ + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); + + /* Enable clock output pin */ + phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); + } + + if (phydev->drv->config) + phydev->drv->config(phydev); return 0; } @@ -116,7 +139,7 @@ int board_eth_init(bd_t *bis) { int ret = 0; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR, + if (designware_initialize(CONFIG_SPEAR_ETHBASE, PHY_INTERFACE_MODE_GMII) >= 0) ret++;