X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ft3corp%2Finit.S;h=7ae9c43924e43041c1e3345686172d00c2879500;hb=d25ba89e8b2b80c7229658b9fabdf96e9af64e01;hp=4a4217fc8e817fa60d584f127494e8def7786232;hpb=2271d3ddccfbd4a7640121669ff9b013b1fea361;p=u-boot

diff --git a/board/t3corp/init.S b/board/t3corp/init.S
index 4a4217fc8e..7ae9c43924 100644
--- a/board/t3corp/init.S
+++ b/board/t3corp/init.S
@@ -2,25 +2,10 @@
  * (C) Copyright 2010
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
 #include <config.h>
 #include <asm/mmu.h>
@@ -81,11 +66,13 @@ tlbtab:
 	tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
 
 	/* TLB-entry for FPGA(s) */
-	tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_1M, CONFIG_SYS_FPGA1_BASE, 4,
+	tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4,
 		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_1M, CONFIG_SYS_FPGA2_BASE, 4,
+	tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M,
+		 CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4,
 		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_1M, CONFIG_SYS_FPGA3_BASE, 4,
+	tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4,
 		 AC_RW | SA_IG)
 
 	/* TLB-entry for OCM */