X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ftqc%2Ftqm834x%2Ftqm834x.c;h=d891a3844ca3836284a907faa7e5514840bcdd84;hb=3e4dad50320d20894710276eb09f2057c6985065;hp=106cac2448e8ff99e8da3f538d432c035961e139;hpb=cb5473205206c7f14cbb1e747f28ec75b48826e2;p=u-boot

diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c
index 106cac2448..d891a3844c 100644
--- a/board/tqc/tqm834x/tqm834x.c
+++ b/board/tqc/tqm834x/tqm834x.c
@@ -2,24 +2,7 @@
  * (C) Copyright 2005
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -28,8 +11,10 @@
 #include <asm/mpc8349_pci.h>
 #include <i2c.h>
 #include <miiphy.h>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
 #include <pci.h>
+#include <flash.h>
+#include <mtd/cfi_flash.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -52,16 +37,12 @@ DECLARE_GLOBAL_DATA_PTR;
 #define INITIAL_CS_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
 				CSCONFIG_COL_BIT_9)
 
-/* Global variable used to store detected number of banks */
-int tqm834x_num_flash_banks;
-
 /* External definitions */
 ulong flash_get_size (ulong base, int banknum);
-extern flash_info_t flash_info[];
 
 /* Local functions */
 static int detect_num_flash_banks(void);
-static long int get_ddr_bank_size(short cs, volatile long *base);
+static long int get_ddr_bank_size(short cs, long *base);
 static void set_cs_bounds(short cs, long base, long size);
 static void set_cs_config(short cs, long config);
 static void set_ddr_config(void);
@@ -122,10 +103,10 @@ phys_size_t initdram (int board_type)
 		debug("\nDetecting Bank%d\n", cs);
 
 		bank_size = get_ddr_bank_size(cs,
-			(volatile long*)(CONFIG_SYS_DDR_BASE + size));
+			(long *)(CONFIG_SYS_DDR_BASE + size));
 		size += bank_size;
 
-		debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20);
+		debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20);
 
 		/* exit if less than one bank */
 		if(size < DDR_MAX_SIZE_PER_CS) break;
@@ -190,7 +171,7 @@ static int detect_num_flash_banks(void)
 	ulong bank2_size;
 	ulong total_size;
 
-	tqm834x_num_flash_banks = 2;	/* assume two banks */
+	cfi_flash_num_flash_banks = 2;	/* assume two banks */
 
 	/* Get bank 1 and 2 information */
 	bank1_size = flash_get_size(CONFIG_SYS_FLASH_BASE, 0);
@@ -244,19 +225,19 @@ static int detect_num_flash_banks(void)
 				 * we got the some data reading from Flash.
 				 * There is only one mirrored bank.
 				 */
-				tqm834x_num_flash_banks = 1;
+				cfi_flash_num_flash_banks = 1;
 				total_size = bank1_size;
 			}
 		}
 	}
 
-	debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
+	debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks);
 
 	/* set OR0 and BR0 */
-	im->lbus.bank[0].or = CONFIG_SYS_OR_TIMING_FLASH |
-		(-(total_size) & OR_GPCM_AM);
-	im->lbus.bank[0].br = (CONFIG_SYS_FLASH_BASE & BR_BA) |
-		(BR_MS_GPCM | BR_PS_32 | BR_V);
+	set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH |
+		   (-(total_size) & OR_GPCM_AM));
+	set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
+		   (BR_MS_GPCM | BR_PS_32 | BR_V));
 
 	return (0);
 }
@@ -264,7 +245,7 @@ static int detect_num_flash_banks(void)
 /*************************************************************************
  * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
  */
-static long int get_ddr_bank_size(short cs, volatile long *base)
+static long int get_ddr_bank_size(short cs, long *base)
 {
 	/* This array lists all valid DDR SDRAM configurations, with
 	 * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
@@ -335,7 +316,7 @@ static long int get_ddr_bank_size(short cs, volatile long *base)
  */
 static void set_cs_bounds(short cs, long base, long size)
 {
-	debug("Setting bounds %08x, %08x for cs %d\n", base, size, cs);
+	debug("Setting bounds %08lx, %08lx for cs %d\n", base, size, cs);
 	if(size == 0){
 		im->ddr.csbnds[cs].csbnds = 0x00000000;
 	} else {
@@ -353,7 +334,7 @@ static void set_cs_bounds(short cs, long base, long size)
  */
 static void set_cs_config(short cs, long config)
 {
-	debug("Setting config %08x for cs %d\n", config, cs);
+	debug("Setting config %08lx for cs %d\n", config, cs);
 	im->ddr.cs_config[cs] = config;
 	SYNC;
 }
@@ -431,3 +412,16 @@ static void set_ddr_config(void) {
 #endif
 	}
 }
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif	/* CONFIG_PCI */
+
+	return 0;
+}
+#endif	/* CONFIG_OF_BOARD_SETUP */