X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Ftrizepsiv%2Fconxs.c;h=129119528fe960215cd8a9acd6055a3558b2d395;hb=f2f7745825ee5f6bae5b480c8e9c6641a7ffa73b;hp=7c6c8550074dbb5e9d7be65b1cccd609f339f4c3;hpb=b90296fc39a33f84bb2b0aa79bf997be495ba791;p=u-boot

diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c
index 7c6c855007..129119528f 100644
--- a/board/trizepsiv/conxs.c
+++ b/board/trizepsiv/conxs.c
@@ -33,6 +33,9 @@
 
 #include <common.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa.h>
+#include <netdev.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -43,33 +46,42 @@ extern struct serial_device serial_ffuart_device;
 extern struct serial_device serial_btuart_device;
 extern struct serial_device serial_stuart_device;
 
+#if CONFIG_MK_POLARIS
+#define BOOT_CONSOLE	"serial_stuart"
+#else
+#define BOOT_CONSOLE	"serial_ffuart"
+#endif
 /* ------------------------------------------------------------------------- */
 
 /*
  * Miscelaneous platform dependent initialisations
  */
 
-void usb_board_init(void)
+int usb_board_init(void)
 {
-	UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
-		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+	writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+		UHCHR);
 
-	UHCHR |= UHCHR_FSBIR;
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
 
-	while (UHCHR & UHCHR_FSBIR);
+	while (readl(UHCHR) & UHCHR_FSBIR)
+		;
 
-	UHCHR &= ~UHCHR_SSE;
-	UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
 
 	/* Clear any OTG Pin Hold */
-	if (PSSR & PSSR_OTGPH)
-		PSSR |= PSSR_OTGPH;
+	if (readl(PSSR) & PSSR_OTGPH)
+		writel(readl(PSSR) | PSSR_OTGPH, PSSR);
 
-	UHCRHDA &= ~(RH_A_NPS);
-	UHCRHDA |= RH_A_PSM;
+	writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
+	writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
 
 	/* Set port power control mask bits, only 3 ports. */
-	UHCRHDB |= (0x7<<17);
+	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+	return 0;
 }
 
 void usb_board_init_fail(void)
@@ -79,23 +91,23 @@ void usb_board_init_fail(void)
 
 void usb_board_stop(void)
 {
-	UHCHR |= UHCHR_FHR;
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 	udelay(11);
-	UHCHR &= ~UHCHR_FHR;
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 
-	UHCCOMS |= 1;
+	writel(readl(UHCCOMS) | 1, UHCCOMS);
 	udelay(10);
 
-	CKEN &= ~CKEN10_USBHOST;
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 
-	puts("Called USB STOP\n");
 	return;
 }
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of ConXS Board */
 	gd->bd->bi_arch_number = 776;
@@ -111,17 +123,14 @@ int board_late_init(void)
 #if defined(CONFIG_SERIAL_MULTI)
 	char *console=getenv("boot_console");
 
-	if ((strcmp(console,"serial_btuart") == 0) ||
-		(strcmp(console,"serial_stuart") == 0) ||
-		(strcmp(console,"serial_ffuart") == 0)) {
-			setenv("stdout",console);
-			setenv("stdin", console);
-			setenv("stderr",console);
-	} else {
-		setenv("stdout", "serial");
-		setenv("stdin", "serial");
-		setenv("stderr", "serial");
+	if ((console == NULL) || (strcmp(console,"serial_btuart") &&
+		strcmp(console,"serial_stuart") &&
+		strcmp(console,"serial_ffuart"))) {
+			console = BOOT_CONSOLE;
 	}
+	setenv("stdout",console);
+	setenv("stdin", console);
+	setenv("stderr",console);
 #endif
 	return 0;
 }
@@ -131,16 +140,22 @@ struct serial_device *default_serial_console (void)
 	return &serial_ffuart_device;
 }
 
-int dram_init (void)
+int dram_init(void)
+{
+	pxa2xx_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+}
 
-	return 0;
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
 }
+#endif