X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fv37%2Fv37.c;h=9c7bad52f3dd5d07d8346f313868a22d5fbfdaa6;hb=588a13f742b6d63ac7d5631af11baa01f3a9e80f;hp=764aff7916fbd810e94c5faaebe19a55b51f930e;hpb=608c91460b37fd9fe0088a0ce813a443f116a8d5;p=u-boot

diff --git a/board/v37/v37.c b/board/v37/v37.c
index 764aff7916..9c7bad52f3 100644
--- a/board/v37/v37.c
+++ b/board/v37/v37.c
@@ -23,7 +23,7 @@
 
 /*
  * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
- * PPCboot port on RPXlite board
+ * U-Boot port on RPXlite board
  *
  * DRAM related UPMA register values are modified.
  * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
@@ -38,39 +38,39 @@ static long int dram_size (void);
 
 /* ------------------------------------------------------------------------- */
 
-#define MBYTE 		(1024*1024)
-#define DRAM_DELAY  	0x00000379  /* DRAM delay count */
+#define MBYTE		(1024*1024)
+#define DRAM_DELAY	0x00000379  /* DRAM delay count */
 #define	_NOT_USED_	0xFFFFCC25
 
 const uint sdram_table[] =
 {
-        /*  single read. (offset 0 in upm RAM) */
-        0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000,
-        0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35,
-
-        /* burst read. (Offset 8 in upm RAM)   */
-        0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000,
-        0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447,
-        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
-        /* single write. (Offset 0x18 in upm RAM) */
-        0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447,
-        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
-        /*  burst write. (Offset 0x20 in upm RAM) */
-        0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000,
-        0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF,
-        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
-        /* Refresh cycle, offset 0x30 */
-        0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-        0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF,
-        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
-        /* Exception, 0ffset 0x3C */
-        0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	/*  single read. (offset 0 in upm RAM) */
+	0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000,
+	0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35,
+
+	/* burst read. (Offset 8 in upm RAM)   */
+	0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000,
+	0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* single write. (Offset 0x18 in upm RAM) */
+	0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/*  burst write. (Offset 0x20 in upm RAM) */
+	0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000,
+	0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Refresh cycle, offset 0x30 */
+	0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Exception, 0ffset 0x3C */
+	0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 };
 /* ------------------------------------------------------------------------- */
 
@@ -90,9 +90,9 @@ int checkboard (void)
 
 /* ------------------------------------------------------------------------- */
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
     volatile memctl8xx_t *memctl = &immap->im_memctl;
     unsigned long temp;
     volatile int delay_cnt;
@@ -121,7 +121,7 @@ long int initdram (int board_type)
 
     delay_cnt = 0;
     while( delay_cnt++ < DRAM_DELAY )
-        ;
+	;
 
     /* Run MRS command in location 5-8 of UPMB */
 
@@ -132,15 +132,15 @@ long int initdram (int board_type)
 
     delay_cnt = 0;
     while( delay_cnt++ < DRAM_DELAY )
-        ;
+	;
 
 #ifdef	CONFIG_CAN_DRIVER
     /* Initialize OR3 / BR3 */
-    memctl->memc_or3 = CFG_OR3_CAN;
-    memctl->memc_br3 = CFG_BR3_CAN;
+    memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
+    memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
 
     /* Initialize MBMR */
-    memctl->memc_mamr = MAMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */
+    memctl->memc_mamr = MAMR_GPL_A4DIS;	/* GPL_A4 ouput line Disable */
 
     /* Initialize UPMB for CAN: single read */
     memctl->memc_mdr = 0xFFFFC004;
@@ -191,7 +191,7 @@ long int initdram (int board_type)
 
 static long int dram_size ()
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
     volatile sysconf8xx_t *siu = &immap->im_siu_conf;
     volatile pcmconf8xx_t *pcm = &immap->im_pcmcia;
     long int		  i, memory=1;
@@ -207,12 +207,12 @@ static long int dram_size ()
 
     switch( memory )
     {
-        case 1:
-            return( 32*MBYTE );
-        case 2:
-            return( 64*MBYTE );
-        default:
-            break;
+	case 1:
+	    return( 32*MBYTE );
+	case 2:
+	    return( 64*MBYTE );
+	default:
+	    break;
     }
     return( 16*MBYTE );
 }