X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fv38b%2Fv38b.c;h=a3377299162e44683ab241f4a4698d10fa5b97b9;hb=ecfc19f31f1fa25f739d11c81d4810f9b35b29aa;hp=99fe7dbc3c4efc1fa5e8b3bc2ebba9b6e3bda042;hpb=d22200f0204ce3210ed47d4e13864ebc60b93918;p=u-boot diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c index 99fe7dbc3c..a337729916 100644 --- a/board/v38b/v38b.c +++ b/board/v38b/v38b.c @@ -5,101 +5,87 @@ * (C) Copyright 2004 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include #include +#include #include -#ifndef CFG_RAMBOOT + +#ifndef CONFIG_SYS_RAMBOOT static void sdram_start(int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; __asm__ volatile ("sync"); /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; __asm__ volatile ("sync"); #if SDRAM_DDR /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE; __asm__ volatile ("sync"); /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; __asm__ volatile ("sync"); #endif /* SDRAM_DDR */ /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; __asm__ volatile ("sync"); /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; __asm__ volatile ("sync"); /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE; __asm__ volatile ("sync"); /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; __asm__ volatile ("sync"); } -#endif /* !CFG_RAMBOOT */ +#endif /* !CONFIG_SYS_RAMBOOT */ -long int initdram(int board_type) +phys_size_t initdram(int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; uint svr, pvr; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ + *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ __asm__ volatile ("sync"); /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; __asm__ volatile ("sync"); #if SDRAM_DDR /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; __asm__ volatile ("sync"); #endif /* SDRAM_DDR */ /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -112,20 +98,20 @@ long int initdram(int board_type) /* set SDRAM CS0 size according to the amount of RAM found */ if (dramsize > 0) - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; else - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ /* find RAM size using SDRAM CS1 only */ if (!dramsize) sdram_start(0); - test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); if (!dramsize) { sdram_start(1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); } if (test1 > test2) { sdram_start(0); @@ -139,28 +125,28 @@ long int initdram(int board_type) /* set SDRAM CS1 size according to the amount of RAM found */ if (dramsize2 > 0) - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); else - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF; if (dramsize >= 0x13) dramsize = (1 << (dramsize - 0x13)) << 20; else dramsize = 0; /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF; if (dramsize2 >= 0x13) dramsize2 = (1 << (dramsize2 - 0x13)) << 20; else dramsize2 = 0; -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* * On MPC5200B we need to set the special configuration delay in the @@ -176,7 +162,7 @@ long int initdram(int board_type) if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + *(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04; __asm__ volatile ("sync"); } @@ -190,31 +176,61 @@ int checkboard (void) return 0; } +int board_early_init_f(void) +{ +#ifdef CONFIG_HW_WATCHDOG + /* + * Enable and configure the direction (output) of PSC3_9 - watchdog + * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's + * Manual. + */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9; +#endif /* CONFIG_HW_WATCHDOG */ + return 0; +} int board_early_init_r(void) { /* - * Now, when we are in RAM, enable flash write access for detection process. - * Note that CS_BOOT cannot be cleared when executing in flash. + * Now, when we are in RAM, enable flash write access for the + * detection process. Note that CS_BOOT cannot be cleared when + * executing in flash. + */ + *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ + + /* + * Enable GPIO_WKUP_7 to "read the status of the actual power + * situation". Default direction is input, so no need to set it + * explicitly. */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7; return 0; } +extern void board_get_enetaddr(uchar *enetaddr); +int misc_init_r(void) +{ + uchar enetaddr[6]; -#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { + board_get_enetaddr(enetaddr); + eth_setenv_enetaddr("ethaddr", enetaddr); + } -#define GPIO_PSC1_4 0x01000000UL + return 0; +} +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) void init_ide_reset(void) { debug("init_ide_reset\n"); /* Configure PSC1_4 as GPIO output for ATA reset */ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; /* Deassert reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; } @@ -223,30 +239,22 @@ void ide_set_reset(int idereset) debug("ide_reset(%d)\n", idereset); if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; /* Make a delay. MPC5200 spec says 25 usec min */ udelay(500000); } else - *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; -} -#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ - - -void led_d4_on(void) -{ - /* TIMER7 as GPIO output low */ - *(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x24; -} - - -void led_d4_off(void) -{ - /* TIMER7 as GPIO output high */ - *(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x34; + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; } +#endif +#ifdef CONFIG_HW_WATCHDOG void hw_watchdog_reset(void) { -/* TODO fill this in */ + /* + * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog + * we need a positive or negative transition on WDI i.e., our PSC3_9. + */ + *(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9; } +#endif /* CONFIG_HW_WATCHDOG */