X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fw7o%2Fw7o.c;h=5c84e65a09db17befe6564cbb429713ca7ccc9aa;hb=65766f38522cc48cab8380f7442cc489ff5020c0;hp=924a449eb8866f7da3a7305607e07f8f5817608f;hpb=c83bf6a2d00ef846c1fb2b0c60540f03ef203125;p=u-boot diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index 924a449eb8..5c84e65a09 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -31,6 +31,7 @@ #include unsigned long get_dram_size (void); +void sdram_init(void); /* * Macros to transform values @@ -41,15 +42,15 @@ unsigned long get_dram_size (void); /* ------------------------------------------------------------------------- */ -int board_pre_init (void) +int board_early_init_f (void) { #if defined(CONFIG_W7OLMG) /* * Setup GPIO pins - reset devices. */ - out32 (IBM405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */ - out32 (IBM405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */ - out32 (IBM405GP_GPIO0_TCR, 0x7f800000); /* setup for output */ + out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */ + out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */ + out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */ /* * IRQ 0-15 405GP internally generated; active high; level sensitive @@ -63,24 +64,24 @@ int board_pre_init (void) * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0, + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ #elif defined(CONFIG_W7OLMC) /* * Setup GPIO pins */ - out32 (IBM405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */ - out32 (IBM405GP_GPIO0_OR, 0x03800000); /* set out pins to default */ - out32 (IBM405GP_GPIO0_TCR, 0x66C00000); /* setup for output */ + out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */ + out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */ + out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */ /* * IRQ 0-15 405GP internally generated; active high; level sensitive @@ -94,16 +95,16 @@ int board_pre_init (void) * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0, + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ #else /* Unknown */ # error "Unknown W7O board configuration" @@ -131,7 +132,7 @@ int checkboard (void) puts ("Board: "); /* VPD data present in I2C EEPROM */ - if (vpd_get_data (CFG_DEF_EEPROM_ADDR, &vpd) == 0) { + if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) { /* * Known board type. */ @@ -151,8 +152,15 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { + /* + * ToDo: Move the asm init routine sdram_init() to this C file, + * or even better use some common ppc4xx code available + * in arch/powerpc/cpu/ppc4xx + */ + sdram_init(); + return get_dram_size (); } @@ -162,17 +170,17 @@ unsigned long get_dram_size (void) int size = 0; /* Get bank Size registers */ - mtdcr (memcfga, mem_mb0cf); /* get bank 0 config reg */ - regs[0] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); /* get bank 0 config reg */ + regs[0] = mfdcr (SDRAM0_CFGDATA); - mtdcr (memcfga, mem_mb1cf); /* get bank 1 config reg */ - regs[1] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); /* get bank 1 config reg */ + regs[1] = mfdcr (SDRAM0_CFGDATA); - mtdcr (memcfga, mem_mb2cf); /* get bank 2 config reg */ - regs[2] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); /* get bank 2 config reg */ + regs[2] = mfdcr (SDRAM0_CFGDATA); - mtdcr (memcfga, mem_mb3cf); /* get bank 3 config reg */ - regs[3] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); /* get bank 3 config reg */ + regs[3] = mfdcr (SDRAM0_CFGDATA); /* compute the size, add each bank if enabled */ for (i = 0; i < 4; i++) { @@ -196,7 +204,7 @@ static void w7o_env_init (VPD * vpd) /* * Read VPD */ - if (vpd_get_data (CFG_DEF_EEPROM_ADDR, vpd) != 0) + if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0) return; /* @@ -207,8 +215,8 @@ static void w7o_env_init (VPD * vpd) (strncmp (vpd->productId, "CMM", 3) == 0))) { char buf[30]; char *eth; - unsigned char *serial = getenv ("serial#"); - unsigned char *ethaddr = getenv ("ethaddr"); + char *serial = getenv ("serial#"); + char *ethaddr = getenv ("ethaddr"); /* Set 'serial#' envvar if serial# isn't set */ if (!serial) { @@ -218,7 +226,7 @@ static void w7o_env_init (VPD * vpd) } /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */ - eth = vpd->ethAddrs[0]; + eth = (char *)(vpd->ethAddrs[0]); if (ethaddr && (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) { /* Now setup ethaddr */ @@ -238,14 +246,14 @@ int misc_init_r (void) #if defined(CONFIG_W7OLMG) unsigned long greg; /* GPIO Register */ - greg = in32 (IBM405GP_GPIO0_OR); + greg = in32 (PPC405GP_GPIO0_OR); /* * XXX - Unreset devices - this should be moved into VxWorks driver code */ greg |= 0x41800000L; /* SAM, PHY, Galileo */ - out32 (IBM405GP_GPIO0_OR, greg); /* set output pins to default */ + out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */ #endif /* CONFIG_W7OLMG */ /*