X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fxaeniax%2Fxaeniax.c;h=40b0f3b30e21b319581350fb58e95da05ec156c4;hb=d7f71414f4296fbea578e80ada1bf2435ed0a2cd;hp=4c19c4dd4ef888a56e748d89c353ca60cb7d49ce;hpb=cd77dd109c4a439519a78c32eddc42bdebc7a61f;p=u-boot

diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c
index 4c19c4dd4e..40b0f3b30e 100644
--- a/board/xaeniax/xaeniax.c
+++ b/board/xaeniax/xaeniax.c
@@ -39,8 +39,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of xaeniax */
 	gd->bd->bi_arch_number = 585;
@@ -58,19 +59,18 @@ int board_late_init(void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	/*	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;*/
-	/*	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;*/
-	/*	gd->bd->bi_dram[2].start = PHYS_SDRAM_3; */
-	/*	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; */
-	/*	gd->bd->bi_dram[3].start = PHYS_SDRAM_4; */
-	/*	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; */
-
-	return 0;
 }
 
 #ifdef CONFIG_CMD_NET