X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fxilinx%2Fzynq%2Fboard.c;h=c8cc2bc93446a1c6392bbd080aa95836f3755be4;hb=f8c1be9816a60d1f627954fe202b502917c69863;hp=b02c364dc9bc6fb7264344ebd818a303e3aad1df;hpb=ec7023db8dc95966919589541f1ca09355a3f7a5;p=u-boot

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index b02c364dc9..c8cc2bc934 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -1,26 +1,11 @@
 /*
  * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #include <netdev.h>
 #include <zynqpl.h>
 #include <asm/arch/hardware.h>
@@ -29,13 +14,15 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_FPGA
-Xilinx_desc fpga;
+xilinx_desc fpga;
 
 /* It can be done differently */
-Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
-Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
-Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
-Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
+xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
+xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
 #endif
 
 int board_init(void)
@@ -49,6 +36,9 @@ int board_init(void)
 	case XILINX_ZYNQ_7010:
 		fpga = fpga010;
 		break;
+	case XILINX_ZYNQ_7015:
+		fpga = fpga015;
+		break;
 	case XILINX_ZYNQ_7020:
 		fpga = fpga020;
 		break;
@@ -58,11 +48,12 @@ int board_init(void)
 	case XILINX_ZYNQ_7045:
 		fpga = fpga045;
 		break;
+	case XILINX_ZYNQ_7100:
+		fpga = fpga100;
+		break;
 	}
 #endif
 
-	icache_enable();
-
 #ifdef CONFIG_FPGA
 	fpga_init();
 	fpga_add(fpga_xilinx, &fpga);
@@ -71,12 +62,47 @@ int board_init(void)
 	return 0;
 }
 
+int board_late_init(void)
+{
+	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+	case ZYNQ_BM_NOR:
+		setenv("modeboot", "norboot");
+		break;
+	case ZYNQ_BM_SD:
+		setenv("modeboot", "sdboot");
+		break;
+	case ZYNQ_BM_JTAG:
+		setenv("modeboot", "jtagboot");
+		break;
+	default:
+		setenv("modeboot", "");
+		break;
+	}
+
+	return 0;
+}
 
-#ifdef CONFIG_CMD_NET
 int board_eth_init(bd_t *bis)
 {
 	u32 ret = 0;
 
+#ifdef CONFIG_XILINX_AXIEMAC
+	ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
+						XILINX_AXIDMA_BASEADDR);
+#endif
+#ifdef CONFIG_XILINX_EMACLITE
+	u32 txpp = 0;
+	u32 rxpp = 0;
+# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
+	txpp = 1;
+# endif
+# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
+	rxpp = 1;
+# endif
+	ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
+			txpp, rxpp);
+#endif
+
 #if defined(CONFIG_ZYNQ_GEM)
 # if defined(CONFIG_ZYNQ_GEM0)
 	ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
@@ -89,7 +115,6 @@ int board_eth_init(bd_t *bis)
 #endif
 	return ret;
 }
-#endif
 
 #ifdef CONFIG_CMD_MMC
 int board_mmc_init(bd_t *bd)
@@ -110,7 +135,28 @@ int board_mmc_init(bd_t *bd)
 
 int dram_init(void)
 {
+#ifdef CONFIG_OF_CONTROL
+	int node;
+	fdt_addr_t addr;
+	fdt_size_t size;
+	const void *blob = gd->fdt_blob;
+
+	node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
+					     "memory", 7);
+	if (node == -FDT_ERR_NOTFOUND) {
+		debug("ZYNQ DRAM: Can't get memory node\n");
+		return -1;
+	}
+	addr = fdtdec_get_addr_size(blob, node, "reg", &size);
+	if (addr == FDT_ADDR_T_NONE || size == 0) {
+		debug("ZYNQ DRAM: Can't get base address or size\n");
+		return -1;
+	}
+	gd->ram_size = size;
+#else
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#endif
+	zynq_ddrc_init();
 
 	return 0;
 }