X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=board%2Fzylonite%2Flowlevel_init.S;h=6f2ad236dd5792290eded39d98ff8696129ce94e;hb=c083e4bab1679814969405dbde9b75b8b97cf850;hp=c3bb4eb67f1bb9ce9180f9d06656fd0af6ee3d2b;hpb=e4558768aef99fe03557ebd2cbdc222467b1e131;p=u-boot

diff --git a/board/zylonite/lowlevel_init.S b/board/zylonite/lowlevel_init.S
index c3bb4eb67f..6f2ad236dd 100644
--- a/board/zylonite/lowlevel_init.S
+++ b/board/zylonite/lowlevel_init.S
@@ -29,7 +29,7 @@
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
 
-DRAM_SIZE:  .long   CFG_DRAM_SIZE
+DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
 
 /* wait for coprocessor write complete */
 .macro CPWAIT reg
@@ -121,7 +121,7 @@ lowlevel_init:
 /*	ldr r2, [r3] */
 /*	cmp r4, r2 */
 /*	bgt 1b */
-	wait #300
+	wait #0x300
 
 mem_init:
 
@@ -235,12 +235,13 @@ mem_init:
 	orr		r1, r1, #0x40000000	@ enable SDRAM for Normal Access
 	str		r1, [r0]
 
+#ifndef CONFIG_SYS_SKIP_DRAM_SCRUB
 	/* scrub/init SDRAM if enabled/present */
-/*	ldr	r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
-/*	ldr	r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
+/*	ldr	r11, =0xa0000000 /\* base address of SDRAM (CONFIG_SYS_DRAM_BASE) *\/ */
+/*	ldr	r12, =0x04000000 /\* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) *\/ */
 /*	mov	r8,r12		 /\* save DRAM size (mk: why???) *\/ */
-	ldr	r8, =0xa0000000	 /* base address of SDRAM (CFG_DRAM_BASE) */
-	ldr	r9, =0x04000000	 /* size of memory to scrub (CFG_DRAM_SIZE) */
+	ldr	r8, =0xa0000000	 /* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */
+	ldr	r9, =0x04000000	 /* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */
 	mov	r0, #0		 /* scrub with 0x0000:0000 */
 	mov	r1, #0
 	mov	r2, #0
@@ -254,6 +255,7 @@ mem_init:
 	stmia	r8!, {r0-r7}
 	beq	15f
 	b	10b
+#endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */
 
 15:
 	/* Mask all interrupts */