X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=common%2Fmemsize.c;h=963e4f35b18059c3d79b30c04ab595281c37273e;hb=b609009801b8a00644926f49b7d0d0cc0d3d8797;hp=dbc812dfc51e65cd351cc1af069714a5f76e5734;hpb=c83bf6a2d00ef846c1fb2b0c60540f03ef203125;p=u-boot

diff --git a/common/memsize.c b/common/memsize.c
index dbc812dfc5..963e4f35b1 100644
--- a/common/memsize.c
+++ b/common/memsize.c
@@ -21,13 +21,23 @@
  * MA 02111-1307 USA
  */
 
+#include <config.h>
+#ifdef __PPC__
+/*
+ * At least on G2 PowerPC cores, sequential accesses to non-existent
+ * memory must be synchronized.
+ */
+# include <asm/io.h>	/* for sync() */
+#else
+# define sync()		/* nothing */
+#endif
 
 /*
  * Check memory range for valid RAM. A simple memory test determines
  * the actually available RAM size between addresses `base' and
  * `base + maxsize'.
  */
-long get_ram_size(volatile long *base, long maxsize)
+long get_ram_size(long *base, long maxsize)
 {
 	volatile long *addr;
 	long           save[32];
@@ -38,20 +48,27 @@ long get_ram_size(volatile long *base, long maxsize)
 
 	for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
 		addr = base + cnt;	/* pointer arith! */
+		sync ();
 		save[i++] = *addr;
+		sync ();
 		*addr = ~cnt;
 	}
 
 	addr = base;
+	sync ();
 	save[i] = *addr;
+	sync ();
 	*addr = 0;
 
+	sync ();
 	if ((val = *addr) != 0) {
 		/* Restore the original data before leaving the function.
 		 */
+		sync ();
 		*addr = save[i];
 		for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
 			addr  = base + cnt;
+			sync ();
 			*addr = save[--i];
 		}
 		return (0);