X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=contrib%2Flibdcc%2Fdcc_stdio.c;h=356ddbdaf2667f3ee2b03c3d0a420db44b3991c9;hb=323aeaf90b969e6041e4c2c478a5d6e574496b17;hp=08a49abf1b82de1cebecbf9d4a2427b361d84d91;hpb=8cb0dae8239a9655eded93b209f18db3fbdbe9d1;p=openocd

diff --git a/contrib/libdcc/dcc_stdio.c b/contrib/libdcc/dcc_stdio.c
index 08a49abf..356ddbda 100644
--- a/contrib/libdcc/dcc_stdio.c
+++ b/contrib/libdcc/dcc_stdio.c
@@ -29,9 +29,9 @@
 #define TARGET_REQ_DEBUGMSG_HEXMSG(size)	(0x01 | ((size & 0xff) << 8))
 #define TARGET_REQ_DEBUGCHAR				0x02
 
-#if defined(__ARM_ARCH_7M__)
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_6SM__)
 
-/* we use the cortex_m3 DCRDR reg to simulate a arm7_9 dcc channel
+/* we use the System Control Block DCRDR reg to simulate a arm7_9 dcc channel
  * DCRDR[7:0] is used by target for status
  * DCRDR[15:8] is used by target for write buffer
  * DCRDR[23:16] is used for by host for status