X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2F74xx_7xx%2Fstart.S;h=42b0f72ac048db8fae7e3824d975d32faa23d52e;hb=f060054dadbbe7027ca088eed806a3ef1f82fdb7;hp=fe08f8e8379df5657872f59f2437ab0217ffced6;hpb=47d1a6e1ed87fe1fb3d737acdb85f69bc3259522;p=u-boot diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S index fe08f8e837..42b0f72ac0 100644 --- a/cpu/74xx_7xx/start.S +++ b/cpu/74xx_7xx/start.S @@ -42,7 +42,12 @@ #include #include +#if !defined(CONFIG_DB64360) && \ + !defined(CONFIG_DB64460) && \ + !defined(CONFIG_CPCI750) && \ + !defined(CONFIG_P3Mx) #include +#endif #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" @@ -68,8 +73,9 @@ GOT_ENTRY(_end_of_vectors) GOT_ENTRY(transfer_to_handler) + GOT_ENTRY(__init_end) GOT_ENTRY(_end) - GOT_ENTRY(.bss) + GOT_ENTRY(__bss_start) END_GOT /* @@ -119,7 +125,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -137,7 +143,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ @@ -158,69 +164,15 @@ ProgramCheck: STD_EXCEPTION(0x900, Decrementer, timer_interrupt) STD_EXCEPTION(0xa00, Trap_0a, UnknownException) STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - - . = 0xc00 -/* - * r0 - SYSCALL number - * r3-... arguments - */ -SystemCall: - addis r11,r0,0 /* get functions table addr */ - ori r11,r11,0 /* Note: this code is patched in trap_init */ - addis r12,r0,0 /* get number of functions */ - ori r12,r12,0 - - cmplw 0, r0, r12 - bge 1f - - rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ - add r11,r11,r0 - lwz r11,0(r11) - - li r12,0xd00-4*3 /* save LR & SRRx */ - mflr r0 - stw r0,0(r12) - mfspr r0,SRR0 - stw r0,4(r12) - mfspr r0,SRR1 - stw r0,8(r12) - - li r12,0xc00+_back-SystemCall - mtlr r12 - mtspr SRR0,r11 - -1: SYNC - rfi - -_back: - - mfmsr r11 /* Disable interrupts */ - li r12,0 - ori r12,r12,MSR_EE - andc r11,r11,r12 - SYNC /* Some chip revs need this... */ - mtmsr r11 - SYNC - - li r12,0xd00-4*3 /* restore regs */ - lwz r11,0(r12) - mtlr r11 - lwz r11,4(r12) - mtspr SRR0,r11 - lwz r11,8(r12) - mtspr SRR1,r11 - - SYNC - rfi - + STD_EXCEPTION(0xc00, SystemCall, UnknownException) STD_EXCEPTION(0xd00, SingleStep, UnknownException) STD_EXCEPTION(0xe00, Trap_0e, UnknownException) STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - /* - * On the MPC8xx, this is a software emulation interrupt. It - * occurs for all unimplemented and illegal instructions. + /* + * On the MPC8xx, this is a software emulation interrupt. It + * occurs for all unimplemented and illegal instructions. */ STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) @@ -267,9 +219,9 @@ boot_warm: #if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx) .long 0x7e00066c /* - * dssall instruction, gas doesn't have it yet - * ...for altivec, data stream stop all this probably - * isn't needed unless we warm (software) reboot U-Boot + * dssall instruction, gas doesn't have it yet + * ...for altivec, data stream stop all this probably + * isn't needed unless we warm (software) reboot U-Boot */ #endif @@ -310,16 +262,16 @@ in_flash: * Cache must be enabled here for stack-in-cache trick. * This means we need to enable the BATS. * This means: - * 1) for the EVB, original gt regs need to be mapped + * 1) for the EVB, original gt regs need to be mapped * 2) need to have an IBAT for the 0xf region, * we are running there! - * Cache should be turned on after BATs, since by default - * everything is write-through. - * The init-mem BAT can be reused after reloc. The old - * gt-regs BAT can be reused after board_init_f calls - * board_pre_init (EVB only). - */ -#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) + * Cache should be turned on after BATs, since by default + * everything is write-through. + * The init-mem BAT can be reused after reloc. The old + * gt-regs BAT can be reused after board_init_f calls + * board_early_init_f (EVB only). + */ +#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx) /* enable address translation */ bl enable_addr_trans sync @@ -364,11 +316,23 @@ invalidate_bats: mtspr IBAT1U, r0 mtspr IBAT2U, r0 mtspr IBAT3U, r0 +#ifdef CONFIG_HIGH_BATS + mtspr IBAT4U, r0 + mtspr IBAT5U, r0 + mtspr IBAT6U, r0 + mtspr IBAT7U, r0 +#endif isync mtspr DBAT0U, r0 mtspr DBAT1U, r0 mtspr DBAT2U, r0 mtspr DBAT3U, r0 +#ifdef CONFIG_HIGH_BATS + mtspr DBAT4U, r0 + mtspr DBAT5U, r0 + mtspr DBAT6U, r0 + mtspr DBAT7U, r0 +#endif isync sync blr @@ -450,6 +414,80 @@ setup_bats: mtspr DBAT3U, r3 isync +#ifdef CONFIG_HIGH_BATS + /* IBAT 4 */ + addis r4, r0, CFG_IBAT4L@h + ori r4, r4, CFG_IBAT4L@l + addis r3, r0, CFG_IBAT4U@h + ori r3, r3, CFG_IBAT4U@l + mtspr IBAT4L, r4 + mtspr IBAT4U, r3 + isync + + /* DBAT 4 */ + addis r4, r0, CFG_DBAT4L@h + ori r4, r4, CFG_DBAT4L@l + addis r3, r0, CFG_DBAT4U@h + ori r3, r3, CFG_DBAT4U@l + mtspr DBAT4L, r4 + mtspr DBAT4U, r3 + isync + + /* IBAT 5 */ + addis r4, r0, CFG_IBAT5L@h + ori r4, r4, CFG_IBAT5L@l + addis r3, r0, CFG_IBAT5U@h + ori r3, r3, CFG_IBAT5U@l + mtspr IBAT5L, r4 + mtspr IBAT5U, r3 + isync + + /* DBAT 5 */ + addis r4, r0, CFG_DBAT5L@h + ori r4, r4, CFG_DBAT5L@l + addis r3, r0, CFG_DBAT5U@h + ori r3, r3, CFG_DBAT5U@l + mtspr DBAT5L, r4 + mtspr DBAT5U, r3 + isync + + /* IBAT 6 */ + addis r4, r0, CFG_IBAT6L@h + ori r4, r4, CFG_IBAT6L@l + addis r3, r0, CFG_IBAT6U@h + ori r3, r3, CFG_IBAT6U@l + mtspr IBAT6L, r4 + mtspr IBAT6U, r3 + isync + + /* DBAT 6 */ + addis r4, r0, CFG_DBAT6L@h + ori r4, r4, CFG_DBAT6L@l + addis r3, r0, CFG_DBAT6U@h + ori r3, r3, CFG_DBAT6U@l + mtspr DBAT6L, r4 + mtspr DBAT6U, r3 + isync + + /* IBAT 7 */ + addis r4, r0, CFG_IBAT7L@h + ori r4, r4, CFG_IBAT7L@l + addis r3, r0, CFG_IBAT7U@h + ori r3, r3, CFG_IBAT7U@l + mtspr IBAT7L, r4 + mtspr IBAT7U, r3 + isync + + /* DBAT 7 */ + addis r4, r0, CFG_DBAT7L@h + ori r4, r4, CFG_DBAT7L@l + addis r3, r0, CFG_DBAT7U@h + ori r3, r3, CFG_DBAT7U@l + mtspr DBAT7L, r4 + mtspr DBAT7U, r3 + isync +#endif + /* bats are done, now invalidate the TLBs */ addis r3, 0, 0x0000 @@ -576,8 +614,8 @@ relocate_code: mr r3, r5 /* Destination Address */ lis r4, CFG_MONITOR_BASE@h /* Source Address */ ori r4, r4, CFG_MONITOR_BASE@l - lis r5, CFG_MONITOR_LEN@h /* Length in Bytes */ - ori r5, r5, CFG_MONITOR_LEN@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ /* @@ -603,8 +641,8 @@ relocate_code: mr r3, r10 /* Destination Address */ lis r4, CFG_MONITOR_BASE@h /* Source Address */ ori r4, r4, CFG_MONITOR_BASE@l - lis r5, CFG_MONITOR_LEN@h /* Length in Bytes */ - ori r5, r5, CFG_MONITOR_LEN@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ #else cmplw cr1,r3,r4 @@ -667,8 +705,8 @@ in_ram: /* * Relocation Function, r14 point to got2+0x8000 * - * Adjust got2 pointers, no need to check for 0, this code - * already puts a few entries in the table. + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. */ li r0,__got2_entries@sectoff@l la r3,GOT(_GOT2_TABLE_) @@ -682,7 +720,7 @@ in_ram: bdnz 1b /* - * Now adjust the fixups and the pointers to the fixups + * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ 2: li r0,__fixup_entries@sectoff@l @@ -702,7 +740,7 @@ in_ram: /* * Now clear BSS segment */ - lwz r3,GOT(.bss) + lwz r3,GOT(__bss_start) lwz r4,GOT(_end) cmplw 0, r3, r4 @@ -716,17 +754,19 @@ in_ram: bne 5b 6: mr r3, r10 /* Destination Address */ +#if defined(CONFIG_AMIGAONEG3SE) || \ + defined(CONFIG_DB64360) || \ + defined(CONFIG_DB64460) || \ + defined(CONFIG_CPCI750) || \ + defined(CONFIG_PPMC7XX) || \ + defined(CONFIG_P3Mx) + mr r4, r9 /* Use RAM copy of the global data */ +#endif bl after_reloc /* not reached - end relocate_code */ /*-----------------------------------------------------------------------*/ - /* Problems accessing "end" in C, so do it here */ - .globl get_endaddr -get_endaddr: - lwz r3,GOT(_end) - blr - /* * Copy exception vector code to low memory * @@ -738,7 +778,7 @@ trap_init: lwz r7, GOT(_start) lwz r8, GOT(_end_of_vectors) - rlwinm r9, r7, 0, 18, 31 /* _start & 0x3FFF */ + li r9, 0x100 /* reset vector always at 0x100 */ cmplw 0, r7, r8 bgelr /* return if r7>=r8 - just in case */