X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Farm1136%2Fmx31%2Fgeneric.c;h=1415d6c2ae01a0552e17fb3b7915ecfbf96f9b02;hb=a32868d6bd8ec07c07deaa64d8232256995dbf42;hp=297d616d5e152d0644f77cca5b36c4c231d6e132;hpb=62479b181460f5bf99517b68059d5ba87908edd3;p=u-boot diff --git a/cpu/arm1136/mx31/generic.c b/cpu/arm1136/mx31/generic.c index 297d616d5e..1415d6c2ae 100644 --- a/cpu/arm1136/mx31/generic.c +++ b/cpu/arm1136/mx31/generic.c @@ -27,8 +27,8 @@ static u32 mx31_decode_pll(u32 reg, u32 infreq) { u32 mfi = (reg >> 10) & 0xf; - u32 mfn = reg & 0x3f; - u32 mfd = (reg >> 16) & 0x3f; + u32 mfn = reg & 0x3ff; + u32 mfd = (reg >> 16) & 0x3ff; u32 pd = (reg >> 26) & 0xf; mfi = mfi <= 5 ? 5 : mfi; @@ -39,7 +39,7 @@ static u32 mx31_decode_pll(u32 reg, u32 infreq) (mfd * pd)) << 10; } -u32 mx31_get_mpl_dpdgck_clk(void) +static u32 mx31_get_mpl_dpdgck_clk(void) { u32 infreq; @@ -48,9 +48,10 @@ u32 mx31_get_mpl_dpdgck_clk(void) else infreq = CONFIG_MX31_HCLK_FREQ; - return mx31_decode_pll(__REG(CCM_MPCTL), infreq); } + return mx31_decode_pll(__REG(CCM_MPCTL), infreq); +} -u32 mx31_get_mcu_main_clk(void) +static u32 mx31_get_mcu_main_clk(void) { /* For now we assume mpl_dpdgck_clk == mcu_main_clk * which should be correct for most boards @@ -72,7 +73,7 @@ u32 mx31_get_ipg_clk(void) void mx31_dump_clocks(void) { u32 cpufreq = mx31_get_mcu_main_clk(); - printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000); + printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000); printf("ipg clock : %dHz\n", mx31_get_ipg_clk()); } @@ -80,17 +81,17 @@ void mx31_gpio_mux(unsigned long mode) { unsigned long reg, shift, tmp; - reg = IOMUXC_BASE + (mode & 0xfc); + reg = IOMUXC_BASE + (mode & 0x1fc); shift = (~mode & 0x3) * 8; tmp = __REG(reg); tmp &= ~(0xff << shift); - tmp |= ((mode >> 8) & 0xff) << shift; + tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift; __REG(reg) = tmp; } #if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) +int print_cpuinfo (void) { printf("CPU: Freescale i.MX31 at %d MHz\n", mx31_get_mcu_main_clk() / 1000000);