X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Farm720t%2Fcpu.c;h=60c1aa90b6b97d6f133b62a3e7820df47ff8af03;hb=19bf91f9628f80a55d4f171df71041574882b3d6;hp=5421aff7def4569b2caa9237eb81b94d4bad6abf;hpb=3ec924a3cb7bc3b37be9adec695d7c3d563b3d2c;p=u-boot

diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c
index 5421aff7de..60c1aa90b6 100644
--- a/cpu/arm720t/cpu.c
+++ b/cpu/arm720t/cpu.c
@@ -57,7 +57,7 @@ int cleanup_before_linux (void)
 	 * and we set the CPU-speed to 73 MHz - see start.S for details
 	 */
 
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
 	unsigned long i;
 
 	disable_interrupts ();
@@ -73,9 +73,11 @@ int cleanup_before_linux (void)
 	/* go to high speed */
 	IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73;
 #endif
-#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B)
+#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292)
 	disable_interrupts ();
 	/* Nothing more needed */
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+	/* No cleanup before linux for IntegratorAP/CM720T as yet */
 #else
 #error No cleanup_before_linux() defined for this CPU type
 #endif
@@ -95,7 +97,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  *
  */
 
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM)
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
 /* read co-processor 15, register #1 (control register) */
 static unsigned long read_p15_c1(void)
 {
@@ -245,6 +247,12 @@ int dcache_status (void)
 	return icache_status();
 }
 
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+	/* No specific cache setup for IntegratorAP/CM720T as yet */
+	void icache_enable (void)
+	{
+	}
+#elif defined(CONFIG_LPC2292) /* just to satisfy the compiler */
 #else
 #error No icache/dcache enable/disable functions defined for this CPU type
 #endif