X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Farm920t%2Fstart.S;h=346f0d09ea77a18b2c9a7b2a3d08a078a9aa4741;hb=e862ed1c22a9aa79835fc4b5f57b4261196a7fac;hp=0e372d0e4ceb5ebcef10ddeff9355eaf9b16cd69;hpb=356a0d9f3123b57392935febd300ce32e63f1278;p=u-boot

diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index 0e372d0e4c..346f0d09ea 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -118,20 +118,17 @@ reset:
 
 /* turn off the watchdog */
 #if defined(CONFIG_S3C2400)
-#define pWTCON		0x15300000
-/* Interupt-Controller base addresses */
-#define INTMSK		0x14400008
-/* clock divisor register */
-#define CLKDIVN		0x14800014
+# define pWTCON		0x15300000
+# define INTMSK		0x14400008	/* Interupt-Controller base addresses */
+# define CLKDIVN	0x14800014	/* clock divisor register */
 #elif defined(CONFIG_S3C2410)
-#define pWTCON		0x53000000
-/* Interupt-Controller base addresses */
-#define INTMSK		0x4A000008
-#define INTSUBMSK	0x4A00001C
-/* clock divisor register */
-#define CLKDIVN		0x4C000014
+# define pWTCON		0x53000000
+# define INTMSK		0x4A000008	/* Interupt-Controller base addresses */
+# define INTSUBMSK	0x4A00001C
+# define CLKDIVN	0x4C000014	/* clock divisor register */
 #endif
 
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
 	ldr     r0, =pWTCON
 	mov     r1, #0x0
 	str     r1, [r0]
@@ -142,26 +139,28 @@ reset:
 	mov	r1, #0xffffffff
 	ldr	r0, =INTMSK
 	str	r1, [r0]
-#if defined(CONFIG_S3C2410)
+# if defined(CONFIG_S3C2410)
 	ldr	r1, =0x3ff
 	ldr	r0, =INTSUBMSK
 	str	r1, [r0]
-#endif
+# endif
 
 	/* FCLK:HCLK:PCLK = 1:2:4 */
 	/* default FCLK is 120 MHz ! */
 	ldr	r0, =CLKDIVN
 	mov	r1, #3
 	str	r1, [r0]
+#endif	/* CONFIG_S3C2400 || CONFIG_S3C2410 */
 
 	/*
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#ifdef CONFIG_INIT_CRITICAL
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
 #endif
 
+#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 relocate:				/* relocate U-Boot to RAM	    */
 	adr	r0, _start		/* r0 <- current position of code   */
 	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
@@ -178,6 +177,7 @@ copy_loop:
 	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
 	cmp	r0, r2			/* until source end addreee [r2]    */
 	ble	copy_loop
+#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
 
 	/* Set up the stack						    */
 stack_setup:
@@ -197,7 +197,7 @@ clear_bss:
 clbss_l:str	r2, [r0]		/* clear loop...                    */
 	add	r0, r0, #4
 	cmp	r0, r1
-	bne	clbss_l
+	ble	clbss_l
 
 #if 0
 	/* try doing this stuff after the relocation */
@@ -237,6 +237,7 @@ _start_armboot:	.word start_armboot
  */
 
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
@@ -255,18 +256,16 @@ cpu_init_crit:
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
 	mcr	p15, 0, r0, c1, c0, 0
 
-
 	/*
 	 * before relocating, we have to setup RAM timing
 	 * because memory timing is board-dependend, you will
-	 * find a memsetup.S in your board directory.
+	 * find a lowlevel_init.S in your board directory.
 	 */
 	mov	ip, lr
-	bl	memsetup
+	bl	lowlevel_init
 	mov	lr, ip
-
 	mov	pc, lr
-
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 
 /*
  *************************************************************************
@@ -433,39 +432,3 @@ fiq:
 	bl 	do_fiq
 
 #endif
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-#ifdef CONFIG_S3C2400
-	bl	disable_interrupts
-# ifdef CONFIG_TRAB
-	bl	disable_vfd
-# endif
-	ldr	r1, _rWTCON
-	ldr	r2, _rWTCNT
-	/* Disable watchdog */
-	mov	r3, #0x0000
-	str	r3, [r1]
-	/* Initialize watchdog timer count register */
-	mov	r3, #0x0001
-	str	r3, [r2]
-	/* Enable watchdog timer; assert reset at timer timeout */
-	mov	r3, #0x0021
-	str	r3, [r1]
-_loop_forever:
-	b	_loop_forever
-_rWTCON:
-	.word	0x15300000
-_rWTCNT:
-	.word	0x15300008
-#else /* ! CONFIG_S3C2400 */
-	mov     ip, #0
-	mcr     p15, 0, ip, c7, c7, 0           @ invalidate cache
-	mcr     p15, 0, ip, c8, c7, 0           @ flush TLB (v4)
-	mrc     p15, 0, ip, c1, c0, 0           @ get ctrl register
-	bic     ip, ip, #0x000f                 @ ............wcam
-	bic     ip, ip, #0x2100                 @ ..v....s........
-	mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
-	mov     pc, r0
-#endif /* CONFIG_S3C2400 */