X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fixp%2Fcpu.c;h=2c7d5a01be7ec25b6482e191bdbe216c41017875;hb=d9ee843d54c54776e1fdb86336ce554906a87331;hp=d12e8bd6c27cec8ec7193d60a4c0d2de629d1722;hpb=2d5b561e2bfdee8552a99b2cf93016cce2a74895;p=u-boot

diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c
index d12e8bd6c2..2c7d5a01be 100644
--- a/cpu/ixp/cpu.c
+++ b/cpu/ixp/cpu.c
@@ -34,25 +34,60 @@
 #include <command.h>
 #include <asm/arch/ixp425.h>
 
+ulong loops_per_jiffy;
+
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo (void)
+{
+	unsigned long id;
+	int speed = 0;
+
+	asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id));
+
+	puts("CPU:   Intel IXP425 at ");
+	switch ((id & 0x000003f0) >> 4) {
+	case 0x1c:
+		loops_per_jiffy = 887467;
+		speed = 533;
+		break;
+
+	case 0x1d:
+		loops_per_jiffy = 666016;
+		speed = 400;
+		break;
+
+	case 0x1f:
+		loops_per_jiffy = 442901;
+		speed = 266;
+		break;
+	}
+
+	if (speed)
+		printf("%d MHz\n", speed);
+	else
+		puts("unknown revision\n");
+
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
 int cpu_init (void)
 {
 	/*
-	 * setup up stack if necessary
+	 * setup up stacks if necessary
 	 */
-/*
-
-  FIXME: the stack is _below_ the uboot code!!
-
 #ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_end +
-			CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
-	FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
-	_armboot_real_end = FIQ_STACK_START + 4;
-#else
-	_armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
+	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+#endif
+
+#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI)
+	pci_init();
 #endif
-*/
-   pci_init();
 	return 0;
 }
 
@@ -82,9 +117,7 @@ int cleanup_before_linux (void)
 
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	extern void reset_cpu (ulong addr);
-
-	printf ("reseting ...\n");
+	printf ("resetting ...\n");
 
 	udelay (50000);				/* wait 50 ms */
 	disable_interrupts ();
@@ -154,7 +187,31 @@ int dcache_status (void)
 }
 
 /* FIXME */
+/*
 void pci_init(void)
 {
 	return;
 }
+*/
+
+#ifdef CONFIG_BOOTCOUNT_LIMIT
+
+void bootcount_store (ulong a)
+{
+	volatile ulong *save_addr = (volatile ulong *)(CFG_BOOTCOUNT_ADDR);
+
+	save_addr[0] = a;
+	save_addr[1] = BOOTCOUNT_MAGIC;
+}
+
+ulong bootcount_load (void)
+{
+	volatile ulong *save_addr = (volatile ulong *)(CFG_BOOTCOUNT_ADDR);
+
+	if (save_addr[1] != BOOTCOUNT_MAGIC)
+		return 0;
+	else
+		return save_addr[0];
+}
+
+#endif /* CONFIG_BOOTCOUNT_LIMIT */