X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fmcf52x2%2Fstart.S;h=2e8ecfbe68c0985426ca9f25a7e6733251cb94c3;hb=56844a22b76c719e600047e23b80465a44d76abd;hp=8ae9591b8ac36d4f995552e5ecca5279a6d9cd41;hpb=eacbd317757327e8e7f018f5701c950429c4c6ae;p=u-boot diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 8ae9591b8a..2e8ecfbe68 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -55,11 +55,13 @@ */ _vectors: -#ifndef CONFIG_M5271 -.long 0x00000000, _START +.long 0x00000000 /* Flash offset is 0 until we setup CS0 */ +#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE) +.long _start - TEXT_BASE #else -.long 0x00000000, 0x400 /* Flash offset is 0 until we setup CS0 */ +.long _START #endif + .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT @@ -100,21 +102,24 @@ _vectors: .text + +#if defined(CFG_INT_FLASH_BASE) && \ + (defined(CONFIG_M5282) || defined(CONFIG_M5281)) + #if (TEXT_BASE == CFG_INT_FLASH_BASE) + .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */ + .long 0xFFFFFFFF /* all sectors protected */ + .long 0x00000000 /* supervisor/User restriction */ + .long 0x00000000 /* programm/data space restriction */ + .long 0x00000000 /* Flash security */ + #endif +#endif .globl _start _start: nop nop move.w #0x2700,%sr - /* if we come from a pre-loader we have no exception table and - * therefore no VBR to set - */ -#if !defined(CONFIG_MONITOR_IS_IN_RAM) - move.l #CFG_FLASH_BASE, %d0 - movec %d0, %VBR -#endif - -#if defined(CONFIG_M5272) || defined(CONFIG_M5249) +#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253) move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */ move.c %d0, %MBAR @@ -126,34 +131,67 @@ _start: move.l #(CFG_INIT_RAM_ADDR + 1), %d0 movec %d0, %RAMBAR0 -#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */ +#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */ -#if defined(CONFIG_M5282) || defined(CONFIG_M5271) +#if defined(CONFIG_M5282) || defined(CONFIG_M5271) /* Initialize IPSBAR */ move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ move.l %d0, 0x40000000 -#ifdef CONFIG_M5282 - /* Initialize FLASHBAR: locate internal Flash and validate it */ - move.l #(CFG_INT_FLASH_BASE + 0x21), %d0 - movec %d0, %RAMBAR0 -#endif - /* Initialize RAMBAR1: locate SRAM and validate it */ move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 movec %d0, %RAMBAR1 -#ifdef CONFIG_M5271 - move.l #(_flash_setup-CFG_FLASH_BASE), %a0 - move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1 - move.l #(CFG_INIT_RAM_ADDR), %a2 + +#if defined(CONFIG_M5282) +#if (TEXT_BASE == CFG_INT_FLASH_BASE) + /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */ + + move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0 + move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1 + move.l #(CFG_INIT_RAM_ADDR), %a2 _copy_flash: - move.l (%a0)+, (%a2)+ - cmp.l %a0, %a1 - bgt.s _copy_flash + move.l (%a0)+, (%a2)+ + cmp.l %a0, %a1 + bgt.s _copy_flash + jmp CFG_INIT_RAM_ADDR + +_flashbar_setup: + /* Initialize FLASHBAR: locate internal Flash and validate it */ + move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 + movec %d0, %FLASHBAR + jmp _after_flashbar_copy.L /* Force jump to absolute address */ +_flashbar_setup_end: + nop +_after_flashbar_copy: +#else + /* Setup code to initialize FLASHBAR, if start from external Memory */ + move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 + movec %d0, %FLASHBAR +#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */ + +#endif +#endif + /* if we come from a pre-loader we have no exception table and + * therefore no VBR to set + */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) +#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE) + move.l #CFG_INT_FLASH_BASE, %d0 +#else + move.l #CFG_FLASH_BASE, %d0 +#endif + movec %d0, %VBR #endif - jmp CFG_INIT_RAM_ADDR -_after_flash_copy: +#ifdef CONFIG_M5275 + /* Initialize IPSBAR */ + move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ + move.l %d0, 0x40000000 +/* movec %d0, %MBAR */ + + /* Initialize RAMBAR: locate SRAM and validate it */ + move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 + movec %d0, %RAMBAR1 #endif #if 0 @@ -174,22 +212,10 @@ _after_flash_copy: bsr cpu_init_f /* run low-level CPU init code (from flash) */ bsr board_init_f /* run low-level board init code (from flash) */ - /* board_init_f() does not return + /* board_init_f() does not return */ /*------------------------------------------------------------------------------*/ -#ifdef CONFIG_M5271 -_flash_setup: - move.l #0x1000, %d0 - move.w %d0, 0x40000080 - move.l #0x2180, %d0 - move.w %d0, 0x4000008A - move.l #0x3f0001, %d0 - move.l %d0, 0x40000084 - jmp _after_flash_copy.L -_flash_setup_end: -#endif - /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -212,7 +238,6 @@ relocate_code: move.l #CFG_MONITOR_BASE, %a1 move.l #__init_end, %a2 move.l %a0, %a3 - /* copy the code to RAM */ 1: move.l (%a1)+, (%a3)+ @@ -260,6 +285,23 @@ clear_bss: cmp.l %a2, %a1 bne 7b +#if defined(CONFIG_M5281) || defined(CONFIG_M5282) + /* patch the 3 accesspoints to 3 ichache_state */ + /* quick and dirty */ + + move.l %a0,%d1 + add.l #(icache_state - CFG_MONITOR_BASE),%d1 + move.l %a0,%a1 + add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1 + move.l %d1,(%a1) + move.l %a0,%a1 + add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1 + move.l %d1,(%a1) + move.l %a0,%a1 + add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1 + move.l %d1,(%a1) +#endif + /* calculate relative jump to board_init_r in ram */ move.l %a0, %a1 add.l #(board_init_r - CFG_MONITOR_BASE), %a1 @@ -267,6 +309,10 @@ clear_bss: /* set parameters for board_init_r */ move.l %a0,-(%sp) /* dest_addr */ move.l %d0,-(%sp) /* gd */ +#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \ + defined(CFG_HALT_BEFOR_RAM_JUMP) + halt +#endif jsr (%a1) /*------------------------------------------------------------------------------*/ @@ -293,6 +339,24 @@ _int_handler: /*------------------------------------------------------------------------------*/ /* cache functions */ +#ifdef CONFIG_M5271 + .globl icache_enable +icache_enable: + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ + movec %d0, %ACR0 /* Enable cache */ + + move.l #0x80000200, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + nop + + move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts +#endif + #ifdef CONFIG_M5272 .globl icache_enable icache_enable: @@ -309,6 +373,25 @@ icache_enable: rts #endif +#if defined(CONFIG_M5275) +/* + * Instruction cache only + */ + .globl icache_enable +icache_enable: + move.l #0x01400000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0x0000c000, %d0 /* Setup SDRAM caching */ + movec %d0, %ACR0 /* Enable cache */ + move.l #0x00000000, %d0 /* No other caching */ + movec %d0, %ACR1 /* Enable cache */ + move.l #0x80400100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + moveq #1, %d0 + move.l %d0, icache_state + rts +#endif + #ifdef CONFIG_M5282 .globl icache_enable icache_enable: @@ -321,18 +404,19 @@ icache_enable: move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/ movec %d0, %CACR /* Enable cache */ moveq #1, %d0 +icache_state_access_1: move.l %d0, icache_state rts #endif -#ifdef CONFIG_M5249 +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) .globl icache_enable icache_enable: /* * Note: The 5249 Documentation doesn't give a bit position for CINV! * From the 5272 and the 5307 documentation, I have deduced that it is * probably CACR[24]. Should someone say something to Motorola? - * ~Jeremy + * ~Jeremy */ move.l #0x01000000, %d0 /* Invalidate whole cache */ move.c %d0,%CACR @@ -355,18 +439,35 @@ icache_disable: movec %d0, %ACR0 /* Enable cache */ movec %d0, %ACR1 /* Enable cache */ moveq #0, %d0 +icache_state_access_2: move.l %d0, icache_state rts .globl icache_status icache_status: - move.l icache_state, %d0 +icache_state_access_3: + move.l #(icache_state), %a0 + move.l (%a0), %d0 rts .data icache_state: - .long 1 + .long 0 /* cache is diabled on inirialization */ + .globl dcache_enable +dcache_enable: + /* dummy function */ + rts + + .globl dcache_disable +dcache_disable: + /* dummy function */ + rts + + .globl dcache_status +dcache_status: + /* dummy function */ + rts /*------------------------------------------------------------------------------*/ @@ -375,3 +476,4 @@ version_string: .ascii U_BOOT_VERSION .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" + .align 4