X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fmcf52x2%2Fstart.S;h=8a83ca5ef7dd933b0ec0e8185892eabb86fcd558;hb=98a9c4d468a942a09ebe8979bec508017f3e4462;hp=b4926e2376b51274faeae4ee7f533f121400f264;hpb=8c725b9364ac92338d659dd31457223ed0e7f538;p=u-boot

diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index b4926e2376..8a83ca5ef7 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -55,7 +55,15 @@
  */
 _vectors:
 
-.long	0x00000000, _START
+.long	0x00000000		/* Flash offset is 0 until we setup CS0 */
+#if defined(CONFIG_R5200)
+.long	0x400
+#elif defined(CONFIG_M5282)
+.long	_start - TEXT_BASE
+#else
+.long	_START
+#endif
+
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
@@ -96,20 +104,23 @@ _vectors:
 
 	.text
 
+
+#if defined(CFG_INT_FLASH_BASE) && \
+    (defined(CONFIG_M5282) || defined(CONFIG_M5281))
+	#if (TEXT_BASE == CFG_INT_FLASH_BASE)
+		.long	0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
+		.long	0xFFFFFFFF /* all sectors protected */
+		.long	0x00000000 /* supervisor/User restriction */
+		.long	0x00000000 /* programm/data space restriction */
+		.long	0x00000000 /* Flash security */
+	#endif
+#endif
 	.globl	_start
 _start:
 	nop
 	nop
 	move.w #0x2700,%sr
 
-	/* if we come from a pre-loader we have no exception table and
-	 * therefore no VBR to set
-	 */
-#if !defined(CONFIG_MONITOR_IS_IN_RAM)
-	move.l	#CFG_FLASH_BASE, %d0
-	movec	%d0, %VBR
-#endif
-
 #if defined(CONFIG_M5272) || defined(CONFIG_M5249)
 	move.l	#(CFG_MBAR + 1), %d0		/* set MBAR address + valid flag */
 	move.c	%d0, %MBAR
@@ -124,26 +135,70 @@ _start:
 	movec	%d0, %RAMBAR0
 #endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */
 
-#ifdef CONFIG_M5282
+#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
 	/* Initialize IPSBAR */
 	move.l	#(CFG_MBAR + 1), %d0		/* set IPSBAR address + valid flag */
 	move.l	%d0, 0x40000000
 
+	/* Initialize RAMBAR1: locate SRAM and validate it */
+	move.l	#(CFG_INIT_RAM_ADDR + 0x21), %d0
+	movec	%d0, %RAMBAR1
+
+#if (TEXT_BASE == CFG_INT_FLASH_BASE)
+	/* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
+
+	move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0
+	move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1
+	move.l #(CFG_INIT_RAM_ADDR), %a2
+_copy_flash:
+	move.l (%a0)+, (%a2)+
+	cmp.l %a0, %a1
+	bgt.s _copy_flash
+	jmp CFG_INIT_RAM_ADDR
+
+_flashbar_setup:
 	/* Initialize FLASHBAR: locate internal Flash and validate it */
 	move.l	#(CFG_INT_FLASH_BASE + 0x21), %d0
 	movec	%d0, %RAMBAR0
+	jmp _after_flashbar_copy.L	/* Force jump to absolute address */
+_flashbar_setup_end:
+	nop
+_after_flashbar_copy:
+#else
+	/* Setup code to initialize FLASHBAR, if start from external Memory */
+	move.l	#(CFG_INT_FLASH_BASE + 0x21), %d0
+	movec	%d0, %RAMBAR0
+#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
 
-	/* Initialize RAMBAR1: locate SRAM and validate it */
-	move.l	#(CFG_INIT_RAM_ADDR + 0x21), %d0
-	movec	%d0, %RAMBAR1
+#endif
+	/* if we come from a pre-loader we have no exception table and
+	 * therefore no VBR to set
+	 */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+	move.l	#CFG_FLASH_BASE, %d0
+	movec	%d0, %VBR
 #endif
 
+#ifdef	CONFIG_R5200
+	move.l	#(_flash_setup-CFG_FLASH_BASE), %a0
+	move.l	#(_flash_setup_end-CFG_FLASH_BASE), %a1
+	move.l	#(CFG_INIT_RAM_ADDR), %a2
+_copy_flash:
+	move.l	(%a0)+, (%a2)+
+	cmp.l	%a0, %a1
+	bgt.s	_copy_flash
+	jmp	CFG_INIT_RAM_ADDR
+_after_flash_copy:
+#endif
+
+#if 0
 	/* invalidate and disable cache */
 	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
 	movec	%d0, %CACR			/* Invalidate cache */
 	move.l	#0, %d0
 	movec	%d0, %ACR0
 	movec	%d0, %ACR1
+#endif
 
 	/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
 	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
@@ -154,10 +209,28 @@ _start:
 	bsr cpu_init_f				/* run low-level CPU init code (from flash) */
 	bsr board_init_f			/* run low-level board init code (from flash) */
 
-	/* board_init_f() does not return
+	/* board_init_f() does not return */
 
 /*------------------------------------------------------------------------------*/
 
+#ifdef	CONFIG_R5200
+_flash_setup:
+	/* CSAR0 */
+	move.l	#((CFG_FLASH_BASE & 0xffff0000) >> 16), %d0
+	move.w	%d0, 0x40000080
+
+	/* CSCR0 */
+	move.l	#0x2180, %d0		/* 8 wait states, 16bit port, auto ack,  */
+	move.w	%d0, 0x4000008A
+
+	/* CSMR0 */
+	move.l	#0x001f0001, %d0	/* 2 MB, valid */
+	move.l	%d0, 0x40000084
+
+	jmp	_after_flash_copy.L
+_flash_setup_end:
+#endif
+
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
@@ -180,7 +253,6 @@ relocate_code:
 	move.l #CFG_MONITOR_BASE, %a1
 	move.l #__init_end, %a2
 	move.l %a0, %a3
-
 	/* copy the code to RAM */
 1:
 	move.l (%a1)+, (%a3)+
@@ -191,14 +263,14 @@ relocate_code:
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.
  */
-	move.l	%a0, %a1
+ 	move.l	%a0, %a1
 	add.l	#(in_ram - CFG_MONITOR_BASE), %a1
 	jmp	(%a1)
 
 in_ram:
 
 clear_bss:
-	/*
+ 	/*
 	 * Now clear BSS segment
 	 */
 	move.l	%a0, %a1
@@ -228,6 +300,23 @@ clear_bss:
 	cmp.l	%a2, %a1
 	bne	7b
 
+#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
+	/* patch the 3 accesspoints to 3 ichache_state */
+	/* quick and dirty */
+
+	move.l	%a0,%d1
+	add.l	#(icache_state - CFG_MONITOR_BASE),%d1
+	move.l	%a0,%a1
+	add.l	#(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1
+	move.l  %d1,(%a1)
+	move.l	%a0,%a1
+	add.l	#(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1
+	move.l  %d1,(%a1)
+	move.l	%a0,%a1
+	add.l	#(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1
+	move.l  %d1,(%a1)
+#endif
+
 	/* calculate relative jump to board_init_r in ram */
 	move.l %a0, %a1
 	add.l #(board_init_r - CFG_MONITOR_BASE), %a1
@@ -235,6 +324,10 @@ clear_bss:
 	/* set parameters for board_init_r */
 	move.l %a0,-(%sp)		/* dest_addr */
 	move.l %d0,-(%sp)		/* gd */
+	#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
+	    defined(CFG_HALT_BEFOR_RAM_JUMP)
+ 		halt
+	#endif
 	jsr	(%a1)
 
 /*------------------------------------------------------------------------------*/
@@ -289,6 +382,7 @@ icache_enable:
 	move.l	#0x80400100, %d0		/* Setup cache mask, data cache disabel*/
 	movec	%d0, %CACR			/* Enable cache */
 	moveq	#1, %d0
+icache_state_access_1:
 	move.l	%d0, icache_state
 	rts
 #endif
@@ -323,18 +417,19 @@ icache_disable:
 	movec	%d0, %ACR0			/* Enable cache */
 	movec	%d0, %ACR1			/* Enable cache */
 	moveq	#0, %d0
+icache_state_access_2:
 	move.l	%d0, icache_state
 	rts
 
 	.globl	icache_status
 icache_status:
+icache_state_access_3:
 	move.l	icache_state, %d0
 	rts
 
 	.data
 icache_state:
-	.long	1
-
+	.long	0	/* cache is diabled on inirialization */
 
 /*------------------------------------------------------------------------------*/