X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fmcf532x%2Fstart.S;h=61be2eac695b122d81782849e198bc8fc8cd1d37;hb=1466ef8db57a2b52efd8c900dd37e7b3840dc263;hp=acd34941a9b8333205c6ec42204829322fc714ac;hpb=ddd104f1ed655eda50c06ba636237a83ed943f34;p=u-boot

diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S
index acd34941a9..61be2eac69 100644
--- a/cpu/mcf532x/start.S
+++ b/cpu/mcf532x/start.S
@@ -131,7 +131,7 @@ _start:
 	movec	%d0, %VBR
 
 	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
-	movec	%d0, %RAMBAR0
+	movec	%d0, %RAMBAR1
 
 	/* invalidate and disable cache */
 	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
@@ -268,10 +268,8 @@ _int_handler:
 icache_enable:
 	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
 	movec	%d0, %CACR			/* Invalidate cache */
-	move.l	#(CFG_SDRAM_BASE + 0xc000), %d0	/* Setup cache mask */
+	move.l	#(CFG_SDRAM_BASE + 0x1c000), %d0
 	movec	%d0, %ACR0			/* Enable cache */
-	move.l	#(CFG_CS0_BASE + 0x0000), %d0	/* Setup cache mask */
-	movec	%d0, %ACR1			/* Enable cache */
 
 	move.l	#0x80000200, %d0		/* Setup cache mask */
 	movec	%d0, %CACR			/* Enable cache */
@@ -284,11 +282,11 @@ icache_enable:
 
 	.globl	icache_disable
 icache_disable:
-	move.l	#0x00000100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
+	move.l	#0x01000000, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Disable cache */
 	clr.l	%d0				/* Setup cache mask */
-	movec	%d0, %ACR0			/* Enable cache */
-	movec	%d0, %ACR1			/* Enable cache */
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
 
 	move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
 	moveq	#0, %d0
@@ -303,7 +301,7 @@ icache_status:
 
 	.globl	icache_invalid
 icache_invalid:
-	move.l	#0x01000000, %d0		/* Setup cache mask */
+	move.l	#0x81000200, %d0		/* Setup cache mask */
 	movec	%d0, %CACR			/* Enable cache */
 	rts