X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fmcf5445x%2Fstart.S;h=738e4a711019c347d0fcdeca590a2575122d0818;hb=84ad688473bec2875e171b71040eb9e033c6c206;hp=d5a7f937f201a9c69331a4111d37af38c87388f8;hpb=156feb90d200f186cdfd856d7f6f1878bb1bec1e;p=u-boot diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S index d5a7f937f2..738e4a7110 100644 --- a/cpu/mcf5445x/start.S +++ b/cpu/mcf5445x/start.S @@ -24,16 +24,12 @@ #include #include #include "version.h" +#include #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" #endif -/* last three long word reserved for cache status */ -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12) -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4) - #define _START _start #define _FAULT _fault @@ -150,8 +146,30 @@ asm_sbf_img_hdr: .long TEXT_BASE /* image to be relocated at */ asm_dram_init: + move.w #0x2700,%sr /* Mask off Interrupt */ + + move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0 + movec %d0, %VBR + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 - movec %d0, %RAMBAR1 /* init Rambar */ + movec %d0, %RAMBAR1 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* dcache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* invalidate and disable cache */ + move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + movec %d0, %ACR2 + movec %d0, %ACR3 + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- @@ -163,10 +181,7 @@ asm_dram_init: move.l #0xFC008004, %a1 move.l #(CONFIG_SYS_CS0_MASK), (%a1) - /* - * Dram Initialization - * a1, a2, and d0 - */ + /* Dram Initialization a1, a2, and d0 */ /* mscr sdram */ move.l #0xFC0A4074, %a1 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1) @@ -209,24 +224,21 @@ dramsz_loop: move.l #0xFC0B8000, %a1 /* Mode */ move.l #0xFC0B8004, %a2 /* Ctrl */ -#ifdef CONFIG_M54455EVB /* Issue PALL */ move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) nop +#ifdef CONFIG_M54455EVB /* Issue LEMR */ move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1) nop move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1) nop - - move.l #1000, %d0 -wait1000: - nop - subq.l #1, %d0 - bne wait1000 #endif + move.l #1000, %d1 + jsr asm_delay + /* Issue PALL */ move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2) nop @@ -243,28 +255,27 @@ wait1000: nop #elif defined(CONFIG_M54451EVB) /* Issue LEMR */ - move.l #(CONFIG_SYS_SDRAM_MODE), (%a2) - nop - move.l #(CONFIG_SYS_SDRAM_EMOD), (%a2) + move.l #(CONFIG_SYS_SDRAM_MODE), (%a1) nop + move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1) #endif - move.l #500, %d0 -wait500: - nop - subq.l #1, %d0 - bne wait500 + move.l #500, %d1 + jsr asm_delay - move.l #(CONFIG_SYS_SDRAM_CTRL), %d0 - and.l #0x7FFFFFFF, %d0 + move.l #(CONFIG_SYS_SDRAM_CTRL), %d1 + and.l #0x7FFFFFFF, %d1 #ifdef CONFIG_M54455EVB - or.l #0x10000c00, %d0 + or.l #0x10000C00, %d1 #elif defined(CONFIG_M54451EVB) - or.l #0x10000000, %d0 + or.l #0x10000C00, %d1 #endif - move.l %d0, (%a2) + move.l %d1, (%a2) nop + move.l #2000, %d1 + jsr asm_delay + /* * DSPI Initialization * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h @@ -274,6 +285,7 @@ wait500: * a4 - Dst addr */ /* Enable pins for DSPI mode - chip-selects are enabled later */ +asm_dspi_init: move.l #0xFC0A4063, %a0 move.b #0x7F, (%a0) @@ -367,39 +379,39 @@ asm_dspi_rd_status: move.b (%a3), %d1 rts + +asm_delay: + nop + subq.l #1, %d1 + bne asm_delay + rts #endif /* CONFIG_CF_SBF */ .text . = 0x400 .globl _start _start: +#if !defined(CONFIG_CF_SBF) nop nop move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ -#if defined(CONFIG_CF_SBF) - move.l #TEXT_BASE, %d0 - movec %d0, %VBR -#else move.l #CONFIG_SYS_FLASH_BASE, %d0 movec %d0, %VBR move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 -#endif /* initialize general use internal ram */ move.l #0, %d0 - move.l #(CACR_STATUS), %a1 /* CACR */ - move.l #(ICACHE_STATUS), %a2 /* icache */ - move.l #(DCACHE_STATUS), %a3 /* dcache */ + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* dcache */ move.l %d0, (%a1) move.l %d0, (%a2) - move.l %d0, (%a3) /* invalidate and disable cache */ - move.l #0x01004100, %d0 /* Invalidate cache cmd */ + move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 @@ -411,6 +423,7 @@ _start: the first c-code */ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- +#endif move.l #__got_start, %a5 /* put relocation table address to a5 */ @@ -522,107 +535,6 @@ _int_handler: addql #4,%sp RESTORE_ALL -/*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d1 - - move.l #0x00040100, %d0 /* Invalidate icache */ - movec %d0, %CACR - - move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 /* Setup icache */ - movec %d0, %ACR2 - - move.l #0x04088020, %d0 /* Enable bcache and icache */ - movec %d0, %CACR - - move.l #(ICACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d0 - - move.l #0xFFF77BFF, %d0 - or.l #0x00040100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Invalidate icache */ - clr.l %d0 - movec %d0, %ACR2 - movec %d0, %ACR3 - - move.l #(ICACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_status -icache_status: - move.l #(ICACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - - .globl icache_invalid -icache_invalid: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d0 - - move.l #0x00040100, %d0 /* Invalidate icache */ - movec %d0, %CACR /* Enable and invalidate cache */ - rts - - .globl dcache_enable -dcache_enable: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d1 - - move.l #0x01040100, %d0 - movec %d0, %CACR /* Invalidate dcache */ - - move.l #0x80088020, %d0 /* Enable bcache and icache */ - movec %d0, %CACR - - move.l #(DCACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_disable -dcache_disable: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d0 - - and.l #0x7FFFFFFF, %d0 - or.l #0x01000000, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Disable dcache */ - clr.l %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(DCACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_invalid -dcache_invalid: - move.l #(CACR_STATUS), %a1 /* read CACR Status */ - move.l (%a1), %d0 - - move.l #0x81088020, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable and invalidate cache */ - rts - - .globl dcache_status -dcache_status: - move.l #(DCACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - /*------------------------------------------------------------------------------*/ .globl version_string