X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fmicroblaze%2Fstart.S;h=3c027ff9bb1c21eced03fa62e606d5c1f624ba70;hb=19bf91f9628f80a55d4f171df71041574882b3d6;hp=bce32978fdd28bdda175157d410587cfdb8d7fe1;hpb=cfc67116a706fd18b8f6a9c11a16753c5626d689;p=u-boot

diff --git a/cpu/microblaze/start.S b/cpu/microblaze/start.S
index bce32978fd..3c027ff9bb 100644
--- a/cpu/microblaze/start.S
+++ b/cpu/microblaze/start.S
@@ -31,6 +31,7 @@
 _start:
 	mts	rmsr, r0	/* disable cache */
 	addi	r1, r0, CFG_INIT_SP_OFFSET
+	addi	r1, r1, -4	/* Decrement SP to top of memory */
 	/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
 	addi	r6, r0, 0xb000	/* hex b000 opcode imm */
 	bslli	r6, r6, 16	/* shift */
@@ -53,6 +54,23 @@ _start:
 	lhu	r7, r1, r0
 	shi	r7, r0, 0x2
 	shi	r6, r0, 0x6
+/*
+ * Copy U-Boot code to TEXT_BASE
+ * solve problem with sbrk_base
+ */
+#if (CFG_RESET_ADDRESS != TEXT_BASE)
+	addi	r4, r0, __end
+	addi	r5, r0, __text_start
+	rsub	r4, r5, r4	/* size = __end - __text_start */
+	addi	r6, r0, CFG_RESET_ADDRESS	/* source address */
+	addi	r7, r0, 0	/* counter */
+4:
+	lw	r8, r6, r7
+	sw	r8, r5, r7
+	addi	r7, r7, 0x4
+	cmp	r8, r4, r7
+	blti	r8, 4b
+#endif
 #endif
 
 #ifdef CFG_USR_EXCEP
@@ -85,6 +103,50 @@ _start:
 	ori	r12, r12, 0xa0
 	mts	rmsr, r12
 
-	/* jumping to board_init */
+clear_bss:
+	/* clear BSS segments */
+	addi	r5, r0, __bss_start
+	addi	r4, r0, __bss_end
+	cmp	r6, r5, r4
+	beqi	r6, 3f
+2:
+	swi     r0, r5, 0 /* write zero to loc */
+	addi    r5, r5, 4 /* increment to next loc */
+	cmp     r6, r5, r4 /* check if we have reach the end */
+	bnei    r6, 2b
+3:	/* jumping to board_init */
 	brai	board_init
 1:	bri	1b
+
+/*
+ * Read 16bit little endian
+ */
+	.text
+	.global	in16
+	.ent	in16
+	.align	2
+in16:	lhu	r3, r0, r5
+	bslli	r4, r3, 8
+	bsrli	r3, r3, 8
+	andi	r4, r4, 0xffff
+	or	r3, r3, r4
+	rtsd	r15, 8
+	sext16	r3, r3
+	.end	in16
+
+/*
+ * Write 16bit little endian
+ * first parameter(r5) - address, second(r6) - short value
+ */
+	.text
+	.global	out16
+	.ent	out16
+	.align	2
+out16:	bslli	r3, r6, 8
+	bsrli	r6, r6, 8
+	andi	r3, r3, 0xffff
+	or	r3, r3, r6
+	sh	r3, r0, r5
+	rtsd	r15, 8
+	or	r0, r0, r0
+	.end	out16