X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fmpc5xxx%2Fcpu_init.c;h=bc6201ec0ac1abf9a2723fe1bf991fc9666b4a52;hb=e18489e8c27e843e337258fb00f2652ff0f43b92;hp=b7e00b3e244e4147be3811447fa312348419c078;hpb=f6e5739a68131998a5ae8aa0cf56a0316f810200;p=u-boot

diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c
index b7e00b3e24..bc6201ec0a 100644
--- a/cpu/mpc5xxx/cpu_init.c
+++ b/cpu/mpc5xxx/cpu_init.c
@@ -123,7 +123,7 @@ void cpu_init_f (void)
 #endif
 
 #if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE)
-	*(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS5_START);
+	*(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS7_START);
 	*(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE);
 	addecr |= (1 << 27);
 #endif
@@ -156,21 +156,21 @@ void cpu_init_f (void)
 	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
 	*(vu_long *)(MPC5XXX_XLBARB + 0x70) = CFG_SDRAM_BASE | 0x1d;
 
-# if defined(CFG_IPBSPEED_133)
+# if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 	/* Motorola reports IPB should better run at 133 MHz. */
 	*(vu_long *)MPC5XXX_ADDECR |= 1;
 	/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
 	addecr = *(vu_long *)MPC5XXX_CDM_CFG;
 	addecr &= ~0x103;
-#  if defined(CFG_PCISPEED_66)
+#  if defined(CFG_PCICLK_EQUALS_IPBCLK_DIV2)
 	/* pci_clk_sel = 0x01 -> IPB_CLK/2 */
 	addecr |= 0x01;
 #  else
 	/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
 	addecr |= 0x02;
-#  endif /* CFG_PCISPEED_66 */
+#  endif /* CFG_PCICLK_EQUALS_IPBCLK_DIV2 */
 	*(vu_long *)MPC5XXX_CDM_CFG = addecr;
-# endif	/* CFG_IPBSPEED_133 */
+# endif	/* CFG_IPBCLK_EQUALS_XLBCLK */
 	/* Configure the XLB Arbiter */
 	*(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff;
 	*(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111;
@@ -198,7 +198,7 @@ int cpu_init_r (void)
 	/* route critical ints to normal ints */
 	*(vu_long *)MPC5XXX_ICTL_EXT |= 0x00000001;
 
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
 	/* load FEC microcode */
 	loadtask(0, 2);
 #endif