X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fmpc824x%2Fstart.S;h=784edc36a0c8b433ed58e735089e32e54c27805b;hb=650632fe4ca09cfd0e5e6a593f2efc02ef87a58c;hp=18b8e612608790909c5d57f7f63bc07ce31a8606;hpb=7c7a23bd5a0bc149d2edd665ec46381726b24e0c;p=u-boot

diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S
index 18b8e61260..784edc36a0 100644
--- a/cpu/mpc824x/start.S
+++ b/cpu/mpc824x/start.S
@@ -73,8 +73,9 @@
 	GOT_ENTRY(_end_of_vectors)
 	GOT_ENTRY(transfer_to_handler)
 
+	GOT_ENTRY(__init_end)
 	GOT_ENTRY(_end)
-	GOT_ENTRY(.bss)
+	GOT_ENTRY(__bss_start)
 #if defined(CONFIG_FADS)
 	GOT_ENTRY(environment)
 #endif
@@ -201,7 +202,6 @@ in_flash:
 	bl	board_init_f	/* run 1st part of board init code (from Flash) */
 
 
-
 	.globl	_start_of_vectors
 _start_of_vectors:
 
@@ -220,7 +220,7 @@ _start_of_vectors:
 /* Alignment exception. */
 	. = EXC_OFF_ALIGN
 Alignment:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
@@ -238,7 +238,7 @@ Alignment:
 /* Program check exception */
 	. = EXC_OFF_PROGRAM
 ProgramCheck:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
@@ -259,74 +259,7 @@ ProgramCheck:
 	STD_EXCEPTION(EXC_OFF_DECR, Decrementer, timer_interrupt)
 	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
 	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
-
-	. = 0xc00
-/*
- * r0 - SYSCALL number
- * r3-... arguments
- */
-SystemCall:
-	addis	r11,r0,0		/* get functions table addr */
-	ori	r11,r11,0		/* Note: this code is patched in trap_init */
-	addis	r12,r0,0		/* get number of functions */
-	ori	r12,r12,0
-
-	cmplw	0, r0, r12
-	bge	1f
-
-	rlwinm	r0,r0,2,0,31		/* fn_addr = fn_tbl[r0] */
-	add	r11,r11,r0
-	lwz	r11,0(r11)
-
-	li	r20,0xd00-4		/* Get stack pointer */
-	lwz	r12,0(r20)
-	subi	r12,r12,12		/* Adjust stack pointer */
-	li	r0,0xc00+_end_back-SystemCall
-	cmplw	0, r0, r12		/* Check stack overflow */
-	bgt	1f
-	stw	r12,0(r20)
-
-	mflr	r0
-	stw	r0,0(r12)
-	mfspr	r0,SRR0
-	stw	r0,4(r12)
-	mfspr	r0,SRR1
-	stw	r0,8(r12)
-
-	li	r12,0xc00+_back-SystemCall
-	mtlr	r12
-	mtspr	SRR0,r11
-
-1:	SYNC
-	rfi
-
-_back:
-
-	mfmsr	r11			/* Disable interrupts */
-	li	r12,0
-	ori	r12,r12,MSR_EE
-	andc	r11,r11,r12
-	SYNC				/* Some chip revs need this... */
-	mtmsr	r11
-	SYNC
-
-	li	r12,0xd00-4		/* restore regs */
-	lwz	r12,0(r12)
-
-	lwz	r11,0(r12)
-	mtlr	r11
-	lwz	r11,4(r12)
-	mtspr	SRR0,r11
-	lwz	r11,8(r12)
-	mtspr	SRR1,r11
-
-	addi	r12,r12,12		/* Adjust stack pointer */
-	li	r20,0xd00-4
-	stw	r12,0(r20)
-
-	SYNC
-	rfi
-_end_back:
+	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 
 	STD_EXCEPTION(EXC_OFF_TRACE, SingleStep, UnknownException)
 
@@ -336,7 +269,7 @@ _end_back:
 	STD_EXCEPTION(EXC_OFF_ITME, InstructionTransMiss, UnknownException)
 	STD_EXCEPTION(EXC_OFF_DLTME, DataLoadTransMiss, UnknownException)
 	STD_EXCEPTION(EXC_OFF_DSTME, DataStoreTransMiss, UnknownException)
-	STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, UnknownException)
+	STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, DebugException)
 	STD_EXCEPTION(EXC_OFF_SMIE, SysManageInt, UnknownException)
 	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
 	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
@@ -542,15 +475,15 @@ relocate_code:
 	mr	r10, r5		/* Save copy of Destination Address	*/
 
 	mr	r3,  r5				/* Destination Address	*/
-#ifdef DEBUG
+#ifdef CFG_RAMBOOT
 	lis	r4, CFG_SDRAM_BASE@h		/* Source      Address	*/
 	ori	r4, r4, CFG_SDRAM_BASE@l
 #else
 	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address	*/
 	ori	r4, r4, CFG_MONITOR_BASE@l
 #endif
-	lis	r5, CFG_MONITOR_LEN@h		/* Length in Bytes	*/
-	ori	r5, r5, CFG_MONITOR_LEN@l
+	lwz	r5, GOT(__init_end)
+	sub	r5, r5, r4
 	li	r6, CFG_CACHELINE_SIZE		/* Cache Line Size	*/
 
 	/*
@@ -593,11 +526,26 @@ relocate_code:
 	stwu	r0,-4(r7)
 	bdnz	3b
 
+4:
+#if !defined(CONFIG_BMW)
+/* Unlock the data cache and invalidate locked area */
+	xor	r0, r0, r0
+	mtspr	1011, r0
+	lis	r4, CFG_INIT_RAM_ADDR@h
+	ori	r4, r4, CFG_INIT_RAM_ADDR@l
+	li	r0, 128
+	mtctr	r0
+41:
+	dcbi	r0, r4
+	addi	r4, r4, 32
+	bdnz	41b
+#endif
+
 /*
  * Now flush the cache: note that we must start from a cache aligned
  * address. Otherwise we might miss one cache line.
  */
-4:	cmpwi	r6,0
+	cmpwi	r6,0
 	add	r5,r3,r5
 	beq	7f		/* Always flush prefetch queue in any case */
 	subi	r0,r6,1
@@ -665,7 +613,7 @@ clear_bss:
 	/*
 	 * Now clear BSS segment
 	 */
-	lwz	r3,GOT(.bss)
+	lwz	r3,GOT(__bss_start)
 	lwz	r4,GOT(_end)
 
 	cmplw	0, r3, r4
@@ -683,12 +631,6 @@ clear_bss:
 	mr	r4, r10		/* Destination Address		*/
 	bl	board_init_r
 
-	/* Problems accessing "end" in C, so do it here */
-	.globl	get_endaddr
-get_endaddr:
-	lwz	r3,GOT(_end)
-	blr
-
 	/*
 	 * Copy exception vector code to low memory
 	 *
@@ -700,7 +642,7 @@ trap_init:
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
-	rlwinm	r9, r7, 0, 18, 31	/* _start & 0x3FFF	*/
+	li	r9, 0x100		/* reset vector always at 0x100 */
 
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */
@@ -845,5 +787,3 @@ setup_bats:
 	blt	1b
 
 	blr
-
-