X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fmpc83xx%2Fpci.c;h=e9965d7df317e0dcf40520c987d42c367a2ce245;hb=ee64d0acc93f4f15850736eafaacdeadd7f12d25;hp=229821887082c46e11806b114f0984ca48408635;hpb=29eaae953476f2bba4d5c7ac097b96cd827c1dff;p=u-boot diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c index 2298218870..e9965d7df3 100644 --- a/cpu/mpc83xx/pci.c +++ b/cpu/mpc83xx/pci.c @@ -28,14 +28,11 @@ #if defined(CONFIG_OF_LIBFDT) #include -#include -#elif defined(CONFIG_OF_FLAT_TREE) -#include +#include #endif #include -#ifdef CONFIG_83XX_GENERIC_PCI #define MAX_BUSES 2 DECLARE_GLOBAL_DATA_PTR; @@ -45,7 +42,7 @@ static int pci_num_buses; static void pci_init_bus(int bus, struct pci_region *reg) { - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; volatile pot83xx_t *pot = immr->ios.pot; volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus]; struct pci_controller *hose = &pci_hose[bus]; @@ -86,7 +83,7 @@ static void pci_init_bus(int bus, struct pci_region *reg) pci_ctrl->pibar1 = 0; pci_ctrl->piebar1 = 0; pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | - PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); + PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1)); i = hose->region_count++; hose->regions[i].bus_start = 0; @@ -97,8 +94,8 @@ static void pci_init_bus(int bus, struct pci_region *reg) hose->first_busno = 0; hose->last_busno = 0xff; - pci_setup_indirect(hose, CFG_IMMR + 0x8300 + bus * 0x80, - CFG_IMMR + 0x8304 + bus * 0x80); + pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80, + CONFIG_SYS_IMMR + 0x8304 + bus * 0x80); pci_register_hose(hose); @@ -121,10 +118,12 @@ static void pci_init_bus(int bus, struct pci_region *reg) #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif +#ifndef CONFIG_PCISLAVE /* * Hose scan. */ hose->last_busno = pci_hose_scan(hose); +#endif } /* @@ -136,7 +135,7 @@ static void pci_init_bus(int bus, struct pci_region *reg) */ void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot) { - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; int i; if (num_buses > MAX_BUSES) { @@ -170,57 +169,73 @@ void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot) pci_init_bus(i, reg[i]); } -#if defined(CONFIG_OF_LIBFDT) -void ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int err; - int tmp[2]; +#ifdef CONFIG_PCISLAVE - if (pci_num_buses < 1) - return; +#define PCI_FUNCTION_CONFIG 0x44 +#define PCI_FUNCTION_CFG_LOCK 0x20 - nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp)); - } +/* + * Unlock the configuration bit so that the host system can begin booting + * + * This should be used after you have: + * 1) Called mpc83xx_pci_init() + * 2) Set up your inbound translation windows to the appropriate size + */ +void mpc83xx_pcislave_unlock(int bus) +{ + struct pci_controller *hose = &pci_hose[bus]; + u32 dev; + u16 reg16; - if (pci_num_buses < 2) - return; + /* Unlock configuration lock in PCI function configuration register */ + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, ®16); + reg16 &= ~(PCI_FUNCTION_CFG_LOCK); + pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16); - nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8600"); - if (nodeoffset >= 0) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp)); - } + /* The configuration bit is now unlocked, so we can scan the bus */ + hose->last_busno = pci_hose_scan(hose); } -#elif CONFIG_OF_FLAT_TREE +#endif + +#if defined(CONFIG_OF_LIBFDT) void ft_pci_setup(void *blob, bd_t *bd) { - u32 *p; - int len; + int nodeoffset; + int tmp[2]; + const char *path; if (pci_num_buses < 1) return; - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); - if (p) { - p[0] = pci_hose[0].first_busno; - p[1] = pci_hose[0].last_busno; - } - - if (pci_num_buses < 2) - return; - - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); - if (p) { - p[0] = pci_hose[1].first_busno; - p[1] = pci_hose[1].last_busno; + nodeoffset = fdt_path_offset(blob, "/aliases"); + if (nodeoffset >= 0) { + path = fdt_getprop(blob, nodeoffset, "pci0", NULL); + if (path) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + + tmp[0] = cpu_to_be32(gd->pci_clk); + do_fixup_by_path(blob, path, "clock-frequency", + &tmp, sizeof(tmp[0]), 1); + } + + if (pci_num_buses < 2) + return; + + path = fdt_getprop(blob, nodeoffset, "pci1", NULL); + if (path) { + tmp[0] = cpu_to_be32(pci_hose[0].first_busno); + tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + do_fixup_by_path(blob, path, "bus-range", + &tmp, sizeof(tmp), 1); + + tmp[0] = cpu_to_be32(gd->pci_clk); + do_fixup_by_path(blob, path, "clock-frequency", + &tmp, sizeof(tmp[0]), 1); + } } } -#endif /* CONFIG_OF_FLAT_TREE */ - -#endif /* CONFIG_83XX_GENERIC_PCI */ +#endif /* CONFIG_OF_LIBFDT */