X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fmpc85xx%2Fcpu.c;h=c78068786650582d0bffeb33d8cb246e7e20e5f1;hb=4e190b03aaf2309bd2e025d1187a2ca880fedc95;hp=74b210cd108232fd34fd30734eb87463c45ccbee;hpb=926662762e5d280f6a9caed8dd9f49be2ebcaf2f;p=u-boot diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 74b210cd10..c780687866 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -25,45 +25,53 @@ * MA 02111-1307 USA */ +#include #include #include #include +#include #include +#include DECLARE_GLOBAL_DATA_PTR; -struct cpu_type { - char name[15]; - u32 soc_ver; +struct cpu_type cpu_type_list [] = { + CPU_TYPE_ENTRY(8533, 8533), + CPU_TYPE_ENTRY(8533, 8533_E), + CPU_TYPE_ENTRY(8536, 8536), + CPU_TYPE_ENTRY(8536, 8536_E), + CPU_TYPE_ENTRY(8540, 8540), + CPU_TYPE_ENTRY(8541, 8541), + CPU_TYPE_ENTRY(8541, 8541_E), + CPU_TYPE_ENTRY(8543, 8543), + CPU_TYPE_ENTRY(8543, 8543_E), + CPU_TYPE_ENTRY(8544, 8544), + CPU_TYPE_ENTRY(8544, 8544_E), + CPU_TYPE_ENTRY(8545, 8545), + CPU_TYPE_ENTRY(8545, 8545_E), + CPU_TYPE_ENTRY(8547, 8547_E), + CPU_TYPE_ENTRY(8548, 8548), + CPU_TYPE_ENTRY(8548, 8548_E), + CPU_TYPE_ENTRY(8555, 8555), + CPU_TYPE_ENTRY(8555, 8555_E), + CPU_TYPE_ENTRY(8560, 8560), + CPU_TYPE_ENTRY(8567, 8567), + CPU_TYPE_ENTRY(8567, 8567_E), + CPU_TYPE_ENTRY(8568, 8568), + CPU_TYPE_ENTRY(8568, 8568_E), + CPU_TYPE_ENTRY(8572, 8572), + CPU_TYPE_ENTRY(8572, 8572_E), }; -#define CPU_TYPE_ENTRY(x) {#x, SVR_##x} +struct cpu_type *identify_cpu(u32 ver) +{ + int i; + for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) + if (cpu_type_list[i].soc_ver == ver) + return &cpu_type_list[i]; -struct cpu_type cpu_type_list [] = { - CPU_TYPE_ENTRY(8533), - CPU_TYPE_ENTRY(8533_E), - CPU_TYPE_ENTRY(8540), - CPU_TYPE_ENTRY(8541), - CPU_TYPE_ENTRY(8541_E), - CPU_TYPE_ENTRY(8543), - CPU_TYPE_ENTRY(8543_E), - CPU_TYPE_ENTRY(8544), - CPU_TYPE_ENTRY(8544_E), - CPU_TYPE_ENTRY(8545), - CPU_TYPE_ENTRY(8545_E), - CPU_TYPE_ENTRY(8547_E), - CPU_TYPE_ENTRY(8548), - CPU_TYPE_ENTRY(8548_E), - CPU_TYPE_ENTRY(8555), - CPU_TYPE_ENTRY(8555_E), - CPU_TYPE_ENTRY(8560), - CPU_TYPE_ENTRY(8567), - CPU_TYPE_ENTRY(8567_E), - CPU_TYPE_ENTRY(8568), - CPU_TYPE_ENTRY(8568_E), - CPU_TYPE_ENTRY(8572), - CPU_TYPE_ENTRY(8572_E), -}; + return NULL; +} int checkcpu (void) { @@ -74,25 +82,40 @@ int checkcpu (void) uint fam; uint ver; uint major, minor; - int i; - u32 ddr_ratio; - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + struct cpu_type *cpu; + char buf1[32], buf2[32]; +#ifdef CONFIG_DDR_CLK_FREQ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) + >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; +#else + u32 ddr_ratio = 0; +#endif svr = get_svr(); ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); +#ifdef CONFIG_MPC8536 + major &= 0x7; /* the msb of this nibble is a mfg code */ +#endif minor = SVR_MIN(svr); +#if (CONFIG_NUM_CPUS > 1) + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + printf("CPU%d: ", pic->whoami); +#else puts("CPU: "); +#endif - for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) - if (cpu_type_list[i].soc_ver == ver) { - puts(cpu_type_list[i].name); - break; - } + cpu = identify_cpu(ver); + if (cpu) { + puts(cpu->name); - if (i == ARRAY_SIZE(cpu_type_list)) + if (IS_E_PROCESSOR(svr)) + puts("E"); + } else { puts("Unknown"); + } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); @@ -111,55 +134,63 @@ int checkcpu (void) puts("Unknown"); break; } + + if (PVR_MEM(pvr) == 0x03) + puts("MC"); + printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); puts("Clock Configuration:\n"); - printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000)); - printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000)); - ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor)); + printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); + switch (ddr_ratio) { case 0x0: - printf(" DDR:%4lu MHz (%lu MT/s data rate), ", - DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); + printf(" DDR:%-4s MHz (%s MT/s data rate), ", + strmhz(buf1, sysinfo.freqDDRBus/2), + strmhz(buf2, sysinfo.freqDDRBus)); break; case 0x7: - printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ", - DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000)); + printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ", + strmhz(buf1, sysinfo.freqDDRBus/2), + strmhz(buf2, sysinfo.freqDDRBus)); break; default: - printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ", - DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); + printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ", + strmhz(buf1, sysinfo.freqDDRBus/2), + strmhz(buf2, sysinfo.freqDDRBus)); break; } -#if defined(CFG_LBC_LCRR) - lcrr = CFG_LBC_LCRR; +#if defined(CONFIG_SYS_LBC_LCRR) + lcrr = CONFIG_SYS_LBC_LCRR; #else { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); lcrr = lbc->lcrr; } #endif clkdiv = lcrr & 0x0f; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { -#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) +#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \ + defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536) /* * Yes, the entire PQ38 family use the same * bit-representation for twice the clock divider values. */ clkdiv *= 2; #endif - printf("LBC:%4lu MHz\n", - DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv); + printf("LBC:%-4s MHz\n", + strmhz(buf1, sysinfo.freqSystemBus / clkdiv)); } else { printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr); } #ifdef CONFIG_CPM2 - printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); + printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); @@ -174,28 +205,33 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { uint pvr; uint ver; + unsigned long val, msr; + pvr = get_pvr(); ver = PVR_VER(pvr); + if (ver & 1){ /* e500 v2 core has reset control register */ volatile unsigned int * rstcr; - rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0); + rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0); *rstcr = 0x2; /* HRESET_REQ */ - }else{ + udelay(100); + } + /* + * Fallthrough if the code above failed * Initiate hard reset in debug control register DBCR0 * Make sure MSR[DE] = 1 */ - unsigned long val, msr; - msr = mfmsr (); - msr |= MSR_DE; - mtmsr (msr); + msr = mfmsr (); + msr |= MSR_DE; + mtmsr (msr); + + val = mfspr(DBCR0); + val |= 0x70000000; + mtspr(DBCR0,val); - val = mfspr(DBCR0); - val |= 0x70000000; - mtspr(DBCR0,val); - } return 1; } @@ -233,7 +269,7 @@ reset_85xx_watchdog(void) #if defined(CONFIG_DDR_ECC) void dma_init(void) { - volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); + volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); dma->satr0 = 0x02c40000; dma->datr0 = 0x02c40000; @@ -243,7 +279,7 @@ void dma_init(void) { } uint dma_check(void) { - volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); + volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); volatile uint status = dma->sr0; /* While the channel is busy, spin */ @@ -262,7 +298,7 @@ uint dma_check(void) { } int dma_xfer(void *dest, uint count, void *src) { - volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); + volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); dma->dar0 = (uint) dest; dma->sar0 = (uint) src; @@ -274,3 +310,82 @@ int dma_xfer(void *dest, uint count, void *src) { return dma_check(); } #endif + +/* + * Configures a UPM. The function requires the respective MxMR to be set + * before calling this function. "size" is the number or entries, not a sizeof. + */ +void upmconfig (uint upm, uint * table, uint size) +{ + int i, mdr, mad, old_mad = 0; + volatile u32 *mxmr; + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile u32 *brp,*orp; + volatile u8* dummy = NULL; + int upmmask; + + switch (upm) { + case UPMA: + mxmr = &lbc->mamr; + upmmask = BR_MS_UPMA; + break; + case UPMB: + mxmr = &lbc->mbmr; + upmmask = BR_MS_UPMB; + break; + case UPMC: + mxmr = &lbc->mcmr; + upmmask = BR_MS_UPMC; + break; + default: + printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm); + hang(); + } + + /* Find the address for the dummy write transaction */ + for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8; + i++, brp += 2, orp += 2) { + + /* Look for a valid BR with selected UPM */ + if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) { + dummy = (volatile u8*)(in_be32(brp) & BR_BA); + break; + } + } + + if (i == 8) { + printf("Error: %s() could not find matching BR\n", __FUNCTION__); + hang(); + } + + for (i = 0; i < size; i++) { + /* 1 */ + out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i); + /* 2 */ + out_be32(&lbc->mdr, table[i]); + /* 3 */ + mdr = in_be32(&lbc->mdr); + /* 4 */ + *(volatile u8 *)dummy = 0; + /* 5 */ + do { + mad = in_be32(mxmr) & MxMR_MAD_MSK; + } while (mad <= old_mad && !(!mad && i == (size-1))); + old_mad = mad; + } + out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM); +} + + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int cpu_eth_init(bd_t *bis) +{ +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85xx_FEC) + tsec_standard_init(bis); +#endif + + return 0; +}