X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fmpc85xx%2Ffdt.c;h=2d36c24b602527690b5bcbcc248f2bc11df5f2d3;hb=1b3e4044a28a3d95b0aad41bdc52482bb2cc9b2b;hp=c159934c5b24630e6c906a748e3dead91e0a9252;hpb=ab06bddb04ed4be50a8f9ad5f94fa23953a734e3;p=u-boot diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index c159934c5b..2d36c24b60 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -28,11 +28,12 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + extern void ft_qe_setup(void *blob); #ifdef CONFIG_MP #include "mp.h" -DECLARE_GLOBAL_DATA_PTR; void ft_fixup_cpu(void *blob, u64 memory_limit) { @@ -79,11 +80,13 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) } #endif -#ifdef CONFIG_L2_CACHE +#define ft_fixup_l3cache(x, y) + +#if defined(CONFIG_L2_CACHE) /* return size in kilobytes */ static inline u32 l2cache_size(void) { - volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; + volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; u32 ver = SVR_SOC_VER(get_svr()); @@ -152,11 +155,70 @@ static inline void ft_fixup_l2cache(void *blob) } fdt_setprop(blob, off, "cache-unified", NULL, 0); fdt_setprop_cell(blob, off, "cache-block-size", line_size); - fdt_setprop_cell(blob, off, "cache-line-size", line_size); fdt_setprop_cell(blob, off, "cache-size", size); fdt_setprop_cell(blob, off, "cache-sets", num_sets); fdt_setprop_cell(blob, off, "cache-level", 2); fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf)); + + /* we dont bother w/L3 since no platform of this type has one */ +} +#elif defined(CONFIG_BACKSIDE_L2_CACHE) +static inline void ft_fixup_l2cache(void *blob) +{ + int off, l2_off, l3_off = -1; + u32 *ph; + u32 l2cfg0 = mfspr(SPRN_L2CFG0); + u32 size, line_size, num_ways, num_sets; + + size = (l2cfg0 & 0x3fff) * 64 * 1024; + num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; + line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32; + num_sets = size / (line_size * num_ways); + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + + while (off != -FDT_ERR_NOTFOUND) { + ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); + + if (ph == NULL) { + debug("no next-level-cache property\n"); + goto next; + } + + l2_off = fdt_node_offset_by_phandle(blob, *ph); + if (l2_off < 0) { + printf("%s: %s\n", __func__, fdt_strerror(off)); + goto next; + } + + fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size); + fdt_setprop_cell(blob, l2_off, "cache-size", size); + fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); + fdt_setprop_cell(blob, l2_off, "cache-level", 2); + fdt_setprop(blob, l2_off, "compatible", "cache", 6); + + if (l3_off < 0) { + ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); + + if (ph == NULL) { + debug("no next-level-cache property\n"); + goto next; + } + l3_off = *ph; + } +next: + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + if (l3_off > 0) { + l3_off = fdt_node_offset_by_phandle(blob, l3_off); + if (l3_off < 0) { + printf("%s: %s\n", __func__, fdt_strerror(off)); + return ; + } + ft_fixup_l3cache(blob, l3_off); + } } #else #define ft_fixup_l2cache(x) @@ -181,7 +243,6 @@ static inline void ft_fixup_cache(void *blob) dnum_sets = dsize / (dline_size * dnum_ways); fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); - fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size); fdt_setprop_cell(blob, off, "d-cache-size", dsize); fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); @@ -192,7 +253,6 @@ static inline void ft_fixup_cache(void *blob) inum_sets = isize / (iline_size * inum_ways); fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); - fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size); fdt_setprop_cell(blob, off, "i-cache-size", isize); fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); @@ -204,32 +264,59 @@ static inline void ft_fixup_cache(void *blob) } +void fdt_add_enet_stashing(void *fdt) +{ + do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1); + + do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); + + do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); +} + void ft_cpu_setup(void *blob, bd_t *bd) { + int off; + int val; + sys_info_t sysinfo; + /* delete crypto node if not on an E-processor */ if (!IS_E_PROCESSOR(get_svr())) fdt_fixup_crypto_node(blob, 0); #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) - fdt_fixup_ethernet(blob, bd); + fdt_fixup_ethernet(blob); + + fdt_add_enet_stashing(blob); #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", bd->bi_busfreq / 8, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "clock-frequency", bd->bi_intfreq, 1); + get_sys_info(&sysinfo); + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]); + fdt_setprop(blob, off, "clock-frequency", &val, 4); + off = fdt_node_offset_by_prop_value(blob, off, "device_type", + "cpu", 4); + } do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); + + do_fixup_by_compat_u32(blob, "fsl,pq3-localbus", + "bus-frequency", gd->lbc_clk, 1); + do_fixup_by_compat_u32(blob, "fsl,elbc", + "bus-frequency", gd->lbc_clk, 1); #ifdef CONFIG_QE ft_qe_setup(blob); #endif -#ifdef CFG_NS16550 +#ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", CFG_NS16550_CLK, 1); + "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif #ifdef CONFIG_CPM2