X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fmpc85xx%2Frelease.S;h=ec5e4daf88f1b09838f4a425f4742fe7acb1024e;hb=56844a22b76c719e600047e23b80465a44d76abd;hp=3b7366ff692c1dbbddd36ac1e3b4382a114bb0f6;hpb=4b7a6dd89633d60dc4b58476d5ce48247f82a3ca;p=u-boot

diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index 3b7366ff69..ec5e4daf88 100644
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -37,6 +37,11 @@ __secondary_start_page:
 	li	r3,0x201
 	mtspr	SPRN_BUCSR,r3
 
+	/* Ensure TB is 0 */
+	li	r3,0
+	mttbl	r3
+	mttbu	r3
+
 	/* Enable/invalidate the I-Cache */
 	mfspr	r0,SPRN_L1CSR1
 	ori	r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
@@ -114,6 +119,7 @@ __secondary_start_page:
 	lwz	r4,ENTRY_ADDR_LOWER(r10)
 	andi.	r11,r4,1
 	bne	2b
+	isync
 
 	/* get the upper bits of the addr */
 	lwz	r11,ENTRY_ADDR_UPPER(r10)
@@ -169,10 +175,10 @@ __secondary_start_page:
 	mtspr	SPRN_SRR1,r13
 	rfi
 
-	.align 3
+	.align L1_CACHE_SHIFT
 	.globl __spin_table
 __spin_table:
-	.space CONFIG_NR_CPUS*ENTRY_SIZE
+	.space CONFIG_NUM_CPUS*ENTRY_SIZE
 
 	/* Fill in the empty space.  The actual reset vector is
 	 * the last word of the page */