X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fmpc86xx%2Fcpu_init.c;h=1fda3fe805226ffce838f355bff9c4e2148df024;hb=b5710d9974f6f0f3ddb4e67d6cccc262ab37049e;hp=c8e46666949adc326045155513fc32e51f40385e;hpb=b706d63559aeec352bc72dd86d7d5423c15f6a60;p=u-boot

diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index c8e4666694..1fda3fe805 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -26,8 +26,13 @@
  * cpu_init.c - low level cpu init
  */
 
+#include <config.h>
 #include <common.h>
 #include <mpc86xx.h>
+#include <asm/mmu.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Breathe some life into the CPU...
@@ -38,7 +43,6 @@
 
 void cpu_init_f(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
 	volatile ccsr_lbc_t *memctl = &immap->im_lbc;
 
@@ -48,6 +52,10 @@ void cpu_init_f(void)
 	/* Clear initial global data */
 	memset ((void *) gd, 0, sizeof (gd_t));
 
+#ifdef CONFIG_FSL_LAW
+	init_laws();
+#endif
+
 	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 	 * addresses - these have to be modified later when FLASH size
 	 * has been determined
@@ -115,3 +123,26 @@ int cpu_init_r(void)
 {
 	return 0;
 }
+
+/* Set up BAT registers */
+void setup_bats(void)
+{
+	write_bat(DBAT0, CFG_DBAT0U, CFG_DBAT0L);
+	write_bat(IBAT0, CFG_IBAT0U, CFG_IBAT0L);
+	write_bat(DBAT1, CFG_DBAT1U, CFG_DBAT1L);
+	write_bat(IBAT1, CFG_IBAT1U, CFG_IBAT1L);
+	write_bat(DBAT2, CFG_DBAT2U, CFG_DBAT2L);
+	write_bat(IBAT2, CFG_IBAT2U, CFG_IBAT2L);
+	write_bat(DBAT3, CFG_DBAT3U, CFG_DBAT3L);
+	write_bat(IBAT3, CFG_IBAT3U, CFG_IBAT3L);
+	write_bat(DBAT4, CFG_DBAT4U, CFG_DBAT4L);
+	write_bat(IBAT4, CFG_IBAT4U, CFG_IBAT4L);
+	write_bat(DBAT5, CFG_DBAT5U, CFG_DBAT5L);
+	write_bat(IBAT5, CFG_IBAT5U, CFG_IBAT5L);
+	write_bat(DBAT6, CFG_DBAT6U, CFG_DBAT6L);
+	write_bat(IBAT6, CFG_IBAT6U, CFG_IBAT6L);
+	write_bat(DBAT7, CFG_DBAT7U, CFG_DBAT7L);
+	write_bat(IBAT7, CFG_IBAT7U, CFG_IBAT7L);
+
+	return;
+}