X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fmpc86xx%2Fspeed.c;h=da5b58b73f29441761d0abd430f8d1f19a879103;hb=dbab0691d2533560f7e91b92ae844046a9ad1df3;hp=8088b870a43a97d511b41649c5c8477e90ce5bde;hpb=12d1ff4c18832d26d2bb8aaab240aaa06c2a83eb;p=u-boot

diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c
index 8088b870a4..da5b58b73f 100644
--- a/cpu/mpc86xx/speed.c
+++ b/cpu/mpc86xx/speed.c
@@ -29,83 +29,21 @@
 #include <mpc86xx.h>
 #include <asm/processor.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef MPC8641HPCN
-/*
- * get_board_sys_clk
- *	Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
- */
+/* used in some defintiions of CONFIG_SYS_CLK_FREQ */
+extern unsigned long get_board_sys_clk(unsigned long dummy);
 
-unsigned long get_board_sys_clk(ulong dummy)
+void get_sys_info(sys_info_t *sysInfo)
 {
-	u8 i, go_bit, rd_clks;
-	ulong val = 0;
-
-	go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
-	go_bit &= 0x01;
-
-	rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
-	rd_clks &= 0x1C;
-
-	/*
-	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
-	 * should we be using the AUX register. Remember, we also set the
-	 * GO bit to boot from the alternate bank on the on-board flash
-	 */
-
-	if (go_bit) {
-		if (rd_clks == 0x1c)
-			i = in8(PIXIS_BASE + PIXIS_AUX);
-		else
-			i = in8(PIXIS_BASE + PIXIS_SPD);
-	} else {
-		i = in8(PIXIS_BASE + PIXIS_SPD);
-	}
-
-	i &= 0x07;
-
-	switch (i) {
-	case 0:
-		val = 33000000;
-		break;
-	case 1:
-		val = 40000000;
-		break;
-	case 2:
-		val = 50000000;
-		break;
-	case 3:
-		val = 66000000;
-		break;
-	case 4:
-		val = 83000000;
-		break;
-	case 5:
-		val = 100000000;
-		break;
-	case 6:
-		val = 134000000;
-		break;
-	case 7:
-		val = 166000000;
-		break;
-	}
-
-	return val;
-}
-
-#endif
-
-void get_sys_info (sys_info_t *sysInfo)
-{
-	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
 	uint plat_ratio, e600_ratio;
 
 	plat_ratio = (gur->porpllsr) & 0x0000003e;
 	plat_ratio >>= 1;
 
-	switch(plat_ratio) {
+	switch (plat_ratio) {
 	case 0x0:
 		sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ;
 		break;
@@ -122,7 +60,7 @@ void get_sys_info (sys_info_t *sysInfo)
 		sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
 		break;
 	default:
-	        sysInfo->freqSystemBus = 0;
+		sysInfo->freqSystemBus = 0;
 		break;
 	}
 
@@ -134,19 +72,19 @@ void get_sys_info (sys_info_t *sysInfo)
 		sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus;
 		break;
 	case 0x19:
-		sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus/2;
+		sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus / 2;
 		break;
 	case 0x20:
 		sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus;
 		break;
 	case 0x39:
-		sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus/2;
+		sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus / 2;
 		break;
 	case 0x28:
 		sysInfo->freqProcessor = 4 * sysInfo->freqSystemBus;
 		break;
 	case 0x1d:
-		sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus/2;
+		sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus / 2;
 		break;
 	default:
 		sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus;
@@ -162,13 +100,26 @@ void get_sys_info (sys_info_t *sysInfo)
 
 int get_clocks(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	sys_info_t sys_info;
 
 	get_sys_info(&sys_info);
 	gd->cpu_clk = sys_info.freqProcessor;
 	gd->bus_clk = sys_info.freqSystemBus;
 
+	/*
+	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
+	 * there is no pattern that can be used to determine the frequency, so
+	 * the only choice is to look up the actual SOC number and use the value
+	 * for that SOC. This information is taken from application note
+	 * AN2919.
+	 */
+#ifdef CONFIG_MPC8610
+	gd->i2c1_clk = sys_info.freqSystemBus;
+#else
+	gd->i2c1_clk = sys_info.freqSystemBus / 2;
+#endif
+	gd->i2c2_clk = gd->i2c1_clk;
+
 	if (gd->cpu_clk != 0)
 		return 0;
 	else