X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fmpc8xx%2Fstart.S;h=eca4b50626dce0f6ef3f175d9e23a9d4d85b6708;hb=8e990cb076a1c77daf3a50cc0df9732135e9eef5;hp=3ebcab46ae1a3af732a9ec7b288a9b616b6966a1;hpb=d94f92cbd7f4a4d3bf0d5d963b709c686e8f6633;p=u-boot

diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S
index 3ebcab46ae..eca4b50626 100644
--- a/cpu/mpc8xx/start.S
+++ b/cpu/mpc8xx/start.S
@@ -27,12 +27,12 @@
  *
  *  The processor starts at 0x00000100 and the code is executed
  *  from flash. The code is organized to be at an other address
- *  in memory, but as long we don't jump around before relocating.
+ *  in memory, but as long we don't jump around before relocating,
  *  board_init lies at a quite high address and when the cpu has
  *  jumped there, everything is ok.
  *  This works because the cpu gives the FLASH (CS0) the whole
  *  address space at startup, and board_init lies as a echo of
- *  the flash somewhere up there in the memorymap.
+ *  the flash somewhere up there in the memory map.
  *
  *  board_init will change CS0 to be positioned at the correct
  *  address and (s)dram will be positioned at address 0
@@ -224,7 +224,7 @@ _start_of_vectors:
 /* Alignment exception. */
 	. = 0x600
 Alignment:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
@@ -242,7 +242,7 @@ Alignment:
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
-	EXCEPTION_PROLOG
+	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */