X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fppc4xx%2F4xx_pci.c;h=c28c7ac86dd64e440ea4e3e601e13ec2f2dfc684;hb=c821b5f120bedf73867513466412587c6912a8f8;hp=a5b9690bec3fceeeca1a894f641ab575e141ea17;hpb=bb66f5613672fc80a6b38a0e1651d893bbe590a5;p=u-boot diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index a5b9690bec..c28c7ac86d 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -46,7 +46,7 @@ * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not * really required after a reset since PMMxMAs are already - * disabled but is a good practice nonetheless. JWB + * disabled but is a good practice nonetheless. JWB * 12-Jun-01 stefan.roese@esd-electronics.com * - PCI host/adapter handling reworked * 09-Jul-01 stefan.roese@esd-electronics.com @@ -531,7 +531,8 @@ int pci_440_init (struct pci_controller *hose) out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ #elif defined(PCIX0_BRDGOPT1) @@ -549,7 +550,8 @@ int pci_440_init (struct pci_controller *hose) out32r( PCIX0_POM0SA, 0 ); /* disable */ out32r( PCIX0_POM1SA, 0 ); /* disable */ out32r( PCIX0_POM2SA, 0 ); /* disable */ -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) out32r( PCIX0_POM0LAL, 0x10000000 ); out32r( PCIX0_POM0LAH, 0x0000000c ); #else @@ -586,7 +588,8 @@ void pci_init_board(void) int busno; busno = pci_440_init (&ppc440_hose); -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) pcie_setup_hoses(busno + 1); #endif }