X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fppc4xx%2F4xx_pcie.c;h=e880c288e1f2e2e01e700034639ab607d4b3110d;hb=9efeadc06f054a9486526d003aee127214155a3f;hp=07fbb0e643f985c2167dea75c4cc2f4160cee095;hpb=156feb90d200f186cdfd856d7f6f1878bb1bec1e;p=u-boot

diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index 07fbb0e643..e880c288e1 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -374,28 +374,35 @@ int ppc4xx_init_pcie(void)
 	/* Set PLL clock receiver to LVPECL */
 	SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
 
-	if (check_error())
+	if (check_error()) {
+		printf("ERROR: failed to set PCIe reference clock receiver --"
+			"PESDR0_PLLLCT1 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT1));
+
 		return -1;
+	}
+
+	/* Did resistance calibration work? */
+	if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) {
+		printf("ERROR: PCIe resistance calibration failed --"
+			"PESDR0_PLLLCT2 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT2));
 
-	if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
-	{
-		printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
-		       SDR_READ(PESDR0_PLLLCT2));
 		return -1;
 	}
 	/* De-assert reset of PCIe PLL, wait for lock */
 	SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
-	udelay(3);
+	udelay(300);	/* 300 uS is maximum time lock should take */
 
 	while (time_out) {
 		if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
 			time_out--;
-			udelay(1);
+			udelay(20);	/* Wait 20 uS more if needed */
 		} else
 			break;
 	}
 	if (!time_out) {
-		printf("PCIE: VCO output not locked\n");
+		printf("ERROR: PCIe PLL VCO output not locked to ref clock --"
+			"PESDR0_PLLLCTS=0x%08x\n", SDR_READ(PESDR0_PLLLCT3));
+
 		return -1;
 	}
 	return 0;