X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=cpu%2Fppc4xx%2Fcpu.c;h=b02f6f4eefb099974902f2269551e23db54c45ee;hb=cd84528f203a28f73e09c11e2737218938eaf71b;hp=94478dbb109ea3c7e3a86907cc96636bc4159219;hpb=887e2ec9ecf49366a60a49b32b73825804909865;p=u-boot

diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 94478dbb10..b02f6f4eef 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -41,6 +41,10 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
+#if defined(CONFIG_BOARD_RESET)
+void board_reset(void);
+#endif
+
 #if defined(CONFIG_440)
 #define FREQ_EBC		(sys_info.freqEPB)
 #else
@@ -84,14 +88,18 @@ int pci_arbiter_enabled(void)
 	return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
 #endif
 
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	unsigned long val;
 
-	mfsdr(sdr_sdstp1, val);
-	return (val & SDR0_SDSTP1_PAE_MASK);
+	mfsdr(sdr_xcr, val);
+	return (val & 0x80000000);
+#endif
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+	unsigned long val;
+
+	mfsdr(sdr_pci0, val);
+	return (val & 0x80000000);
 #endif
 }
 #endif
@@ -192,6 +200,7 @@ int checkcpu (void)
 	char buf[32];
 
 #if !defined(CONFIG_IOP480)
+	char addstr[64] = "";
 	sys_info_t sys_info;
 
 	puts ("CPU:   ");
@@ -307,36 +316,68 @@ int checkcpu (void)
 #endif /* CONFIG_440GR */
 #endif /* CONFIG_440 */
 
-	case PVR_440EPX1_RA:
-		puts("EPx Rev. A - Security/Kasumi support");
+#ifdef CONFIG_440EPX
+	case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
+		puts("EPx Rev. A");
+		strcpy(addstr, "Security/Kasumi support");
+		break;
+
+	case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
+		puts("EPx Rev. A");
+		strcpy(addstr, "No Security/Kasumi support");
+		break;
+#endif /* CONFIG_440EPX */
+
+#ifdef CONFIG_440GRX
+	case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
+		puts("GRx Rev. A");
+		strcpy(addstr, "Security/Kasumi support");
 		break;
 
-	case PVR_440EPX2_RA:
-		puts("EPx Rev. A - No Security/Kasumi support");
+	case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
+		puts("GRx Rev. A");
+		strcpy(addstr, "No Security/Kasumi support");
 		break;
+#endif /* CONFIG_440GRX */
 
-	case PVR_440GRX1_RA:
-		puts("GRx Rev. A - Security/Kasumi support");
+	case PVR_440SP_6_RAB:
+		puts("SP Rev. A/B");
+		strcpy(addstr, "RAID 6 support");
 		break;
 
-	case PVR_440GRX2_RA:
-		puts("GRx Rev. A - No Security/Kasumi support");
+	case PVR_440SP_RAB:
+		puts("SP Rev. A/B");
+		strcpy(addstr, "No RAID 6 support");
 		break;
 
-	case PVR_440SP_RA:
-		puts("SP Rev. A");
+	case PVR_440SP_6_RC:
+		puts("SP Rev. C");
+		strcpy(addstr, "RAID 6 support");
 		break;
 
-	case PVR_440SP_RB:
-		puts("SP Rev. B");
+	case PVR_440SP_RC:
+		puts("SP Rev. C");
+		strcpy(addstr, "No RAID 6 support");
+		break;
+
+	case PVR_440SPe_6_RA:
+		puts("SPe Rev. A");
+		strcpy(addstr, "RAID 6 support");
 		break;
 
 	case PVR_440SPe_RA:
 		puts("SPe Rev. A");
+		strcpy(addstr, "No RAID 6 support");
+		break;
+
+	case PVR_440SPe_6_RB:
+		puts("SPe Rev. B");
+		strcpy(addstr, "RAID 6 support");
 		break;
 
 	case PVR_440SPe_RB:
 		puts("SPe Rev. B");
+		strcpy(addstr, "No RAID 6 support");
 		break;
 
 	default:
@@ -349,13 +390,16 @@ int checkcpu (void)
 	       sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
 	       FREQ_EBC / 1000000);
 
+	if (addstr[0] != 0)
+		printf("       %s\n", addstr);
+
 #if defined(I2C_BOOTROM)
 	printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
 #if defined(SDR0_PINSTP_SHIFT)
 	printf ("       Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
 	printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
-#endif
-#endif
+#endif	/* SDR0_PINSTP_SHIFT */
+#endif	/* I2C_BOOTROM */
 
 #if defined(CONFIG_PCI)
 	printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
@@ -403,7 +447,7 @@ int ppc440spe_revB() {
 	unsigned int pvr;
 
 	pvr = get_pvr();
-	if (pvr == PVR_440SPe_RB)
+	if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
 		return 1;
 	else
 		return 0;
@@ -414,23 +458,19 @@ int ppc440spe_revB() {
 
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)
-	/*give reset to BCSR*/
-	*(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09;
-
+#if defined(CONFIG_BOARD_RESET)
+	board_reset();
+#else
+#if defined(CFG_4xx_RESET_TYPE)
+	mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
 #else
-
 	/*
 	 * Initiate system reset in debug control register DBCR
 	 */
-	__asm__ __volatile__("lis   3, 0x3000" ::: "r3");
-#if defined(CONFIG_440)
-	__asm__ __volatile__("mtspr 0x134, 3");
-#else
-	__asm__ __volatile__("mtspr 0x3f2, 3");
-#endif
+	mtspr(dbcr0, 0x30000000);
+#endif /* defined(CFG_4xx_RESET_TYPE) */
+#endif /* defined(CONFIG_BOARD_RESET) */
 
-#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/
 	return 1;
 }